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1.8 volt intel ? wireless flash memory with 3 volt i/o and sram (w30) 28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary datasheet product features the 1.8 volt intel ? wireless flash memory with 3 volt i/o combines state-of-the-art intel ? flash technology with low power sram to provide the most versatile and compact memory solution for high performance, low power, board constraint memory applications. the 1.8 volt intel wireless flash memory with 3 volt i/o offers a multi-partition, dual-operation flash architecture that enables the device to read from one partition while programming or erasing in another partition. this read-while-write or read-while-erase capability makes it possible to achieve higher data throughput rates as compared to single partition devices and it allows two processors to interleave code execution because program and erase operations can now occur as background processes. the 1.8 volt intel wireless flash memory with 3 volt i/o incorporates a new enhanced factory programming (efp) mode to improve 12 v factory programming performance. this new feature helps eliminate manufacturing bottlenecks associated with programming high density flash devices. compare the efp program time of 3.5 s per word to the standard factory program time of 8.0 s per word and save significant factory programming time for improved factory efficiency. additionally, the 1.8 volt intel wireless flash memory with 3 volt i/o includes block lock-down, programmable wait signal polarity and is supported by an array of software tools. all these features make this product a perfect solution for any demanding memory application. flash performance ? 70 ns initial access speed ? 25 ns page-mode read speed ? 20 ns burst-mode read speed ? burst and page mode in all blocks and across all partition boundaries ? enhanced factory programming: 3.5 s per word program time ? programmable wait signal polarity flash power ? v cc = 1.70 v ? 1.90 v ? v ccq = 2.20 v ? 3.30 v ? standby current = 6 a (typ.) ? read current = 7 ma (4 word burst, typ.) flash software ? 5/9 s (typ.) program/erase suspend latency time ? intel ? flash data integrator (fdi) and common flash interface (cfi) compatible quality and reliability ? operating temperature: ? 25 c to +85 c ? 100k minimum erase cycles ? 0.18 m etox ? vii process flash architecture ? multiple 4-mbit partitions ? dual operation: rww or rwe ? parameter block size = 4-kword ? main block size = 32-kword ? top and bottom parameter devices flash security ? 128-bit protection register: 64 unique device identifier bits; 64 user otp protection register bits ? absolute write protection with v pp at ground ? program and erase lockout during power transitions ? individual and instantaneous block locking/ unlocking with lock-down sram ? 70 ns access speed ? 16-bit data bus ? low voltage data retention ? s-v cc = 2.20 v ? 3.30 v density and packaging ? 32-mbit discrete in vf bga package ? 64-mbit discrete in bga* package ? 56 active ball matrix, 0.75 mm ball-pitch in bga* and vf bga packages ? 32/4-, 64/8- and 128/tbd- mbit (flash + sram) in a 80-ball stacked-csp package (14 mm x 8 mm) ? 16-bit data bus 290702-002 march 2001 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
preliminary information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 1.8 volt intel ? wireless flash memory (with 3 volt i/o and sram) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2000 - 2001. *other names and brands may be claimed as the property of others.
preliminary iii 28f320w30, 28f3204w30, 28f6408w30, 28f640w30 contents 1.0 product introduction .................................................................................................1 1.1 document purpose................................................................................................ 1 1.2 nomenclature ........................................................................................................1 2.0 product description .................................................................................................. 2 2.1 product overview .................................................................................................. 2 2.2 package diagram.................................................................................................. 3 2.3 package dimensions............................................................................................. 4 2.4 signal descriptions................................................................................................ 5 2.5 block diagram ....................................................................................................... 6 2.6 flash memory map................................................................................................ 6 3.0 product operations ................................................................................................... 9 3.1 bus operations...................................................................................................... 9 3.2 flash command definitions .................................................................................. 9 4.0 flash read modes ...................................................................................................12 4.1 read array ..........................................................................................................12 4.1.1 asynchronous mode...............................................................................12 4.1.2 synchronous mode ................................................................................12 4.2 set configuration register (cr)..........................................................................13 4.2.1 read mode (rm)....................................................................................14 4.2.2 first latency count (lc2 ? 0) ..................................................................14 4.2.3 wait signal polarity (wt) .....................................................................16 4.2.4 wait signal function.............................................................................17 4.2.5 data output configuration (doc) ..........................................................17 4.2.6 wait configuration (wc).......................................................................18 4.2.7 burst sequence (bs)..............................................................................19 4.2.8 clock configuration (cc) .......................................................................20 4.2.9 burst wrap (bw) ....................................................................................21 4.2.10 burst length (bl2 ? 0) .............................................................................21 4.3 read query register...........................................................................................21 4.4 read id register.................................................................................................21 4.5 read status register ..........................................................................................22 4.5.1 clear status register .............................................................................24 4.6 read-while-write/erase......................................................................................24 5.0 program and erase voltages ...............................................................................24 5.1 factory program mode........................................................................................24 5.2 programming voltage protection (vpp)..............................................................25 5.3 enhanced factory programming (efp) ..............................................................25 5.3.1 efp requirements and considerations .................................................26 5.3.2 setup phase...........................................................................................26 5.3.3 program phase ......................................................................................26 5.3.4 verify phase ...........................................................................................27 5.3.5 exit phase ..............................................................................................27 5.4 write protection (v pp < v pplk ) ...........................................................................27
28f320w30, 28f3204w30, 28f6408w30, 28f640w30 iv preliminary 6.0 flash erase mode .................................................................................................... 27 6.1 block erase ......................................................................................................... 27 6.2 erase protection (v pp < v pplk ) .......................................................................... 28 7.0 flash suspend/resume modes .......................................................................... 28 7.1 program/erase suspend..................................................................................... 28 7.2 program/erase resume...................................................................................... 28 8.0 flash security modes ............................................................................................. 29 8.1 block lock........................................................................................................... 29 8.2 block unlock ....................................................................................................... 30 8.3 lock-down block ................................................................................................ 30 8.4 block lock operations during erase suspend.................................................... 30 8.5 wp# lock-down control..................................................................................... 30 9.0 flash protection register ..................................................................................... 32 9.1 protection register read .................................................................................... 32 9.2 program protection register ............................................................................... 32 9.3 protection register lock ..................................................................................... 33 10.0 power and reset considerations ...................................................................... 34 10.1 power-up/down characteristics ......................................................................... 34 10.2 power supply decoupling ................................................................................... 34 10.3 flash reset characteristics ................................................................................ 34 11.0 electrical specifications ........................................................................................ 35 11.1 absolute maximum ratings ................................................................................ 35 11.2 extended temperature operation....................................................................... 35 11.3 dc characteristics .............................................................................................. 36 11.4 discrete capacitance (32-mbit vf bga package) ............................................. 38 11.5 stacked capacitance (32/4 and 64/8 stacked-csp package) ........................... 39 12.0 flash ac characteristics ...................................................................................... 40 12.1 flash read operations ....................................................................................... 40 12.2 flash write operations ....................................................................................... 49 12.3 flash program and erase operations................................................................. 51 12.4 reset operations ................................................................................................ 51 13.0 sram ac characteristics ..................................................................................... 53 13.1 sram read operation ....................................................................................... 53 13.2 sram write operation........................................................................................ 55 13.3 sram data retention operation ........................................................................ 56 14.0 ordering information .............................................................................................. 58 appendix a flash write state machine (wsm) ................................................................ 59 appendix b flowcharts ............................................................................................................. 61 appendix c common flash interface ................................................................................. 68
preliminary v 28f320w30, 28f3204w30, 28f6408w30, 28f640w30 revision history date of revision version description 09/19/00 -001 original version 03/14/01 -002 28f3208w30 product references removed (product was discontinued) 28f640w30 product added revised table 2, signal descriptions ( dq 15 ? 0 , adv#, wait, s-ub#, s-lb#, v ccq ) revised section 3.1, bus operations revised table 5, command bus definitions , notes 1 and 2 revised section 4.2.2, first latency count (lc 2?0 ); revised figure 6, data output with lc setting at code 3 ; added figure 7, first access latency configuration revised section 4.2.3, wait signal polarity (wt) added section 4.2.4, wait signal function revised section 4.2.5, data output configuration (doc) added figure 8, data output configuration with wait signal delay revised table 13, status register dws and pws description revised entire section 5.0, program and erase voltages revised entire section 5.3, enhanced factory programming (efp) revised entire section 8.0, flash security modes revised entire section 9.0, flash protection register ; added table 15, simulta- neous operations allowed with the protection register revised section 10.1, power-up/down characteristics revised section 11.3, dc characteristics. c hanged i ccs, i ccws, i cces specs from 18 a to 21a; changed i ccr spec from 12 ma to 15 ma (burst length = 4) added figure 20, wait signal in synchronous non-read array operation wave- form added figure 21, wait signal in asynchronous page-mode read operation waveform added figure 22, wait signal in asynchronous single-word read operation waveform revised figure 23, write waveform revised section 12.4, reset operations clarified section 13.2, sram write operation , note 2 revised section 14.0, ordering information minor text edits

28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 1 1.0 product introduction 1.1 document purpose this document contains information pertaining to the 1.8 volt intel ? wireless flash memory with 3 volt i/o and sram. section 1.0 provides a product introduction. section 2.0 provides a product description. section 3.0 describes general device operations. sections 4.0 through 9.0 describe the flash functionality. section 10 describes device power and reset considerations. section 11.0 describes the device electrical specifications. section 12.0 describes the flash ac characteristics. section 13.0 describes the sram ac characteristics. section 14.0 describes ordering information. 1.2 nomenclature block: a group of flash bits that share common erase circuitry and erase simultaneously. partition: partition is a group of blocks that share erase and program circuitry and a common status register. if one block is erasing or one word is programming, only the status register, rather than array data, is available when any address within the partition is read. main block: a flash block of 32-kwords. parameter block: a flash block of 4-kwords. main partition: a partition that only contains main blocks. parameter partition: a partition that contains both main and parameter blocks. top/bottom parameter device: parameter blocks are located at the top/bottom of the flash memory map. a top/bottom parameter partition contains 15 blocks; 7 main blocks and 8 parameter blocks.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 2 preliminary 2.0 product description 2.1 product overview intel ? 1.8 volt wireless flash memory with 3 volt i/o and sram combines flash and sram into one package. the 1.8 volt intel wireless flash memory with 3 volt i/o divides the flash memory into many separate 4-mbit partitions. by doing this, the device can perform simultaneous read- while-write or read-while-erase operations. with this new architecture, the 1.8 volt intel wireless flash memory with 3 volt i/o can read from one partition while programming or erasing in another partition. this read-while-write or read-while-erase capability greatly increases data throughput performance. each partition contains eight 32-kword blocks, called ? main blocks. ? however, for a top or bottom parameter device, the upper or lower 32-kword block is segmented into eight, separate 4-kword blocks, called ? parameter blocks. ? parameter blocks are ideally suited for frequently updated variables or boot code storage. both main and parameter blocks support page and burst mode reads. the 1.8 volt intel wireless flash memory with 3 volt i/o also incorporates a new enhanced factory programming (efp) mode. in efp mode, this device provides the fastest nor flash factory programming time possible at 3.5 s per data word. this feature can greatly reduce factory flash programming time and thereby increase manufacturing efficiency. the 1.8 volt intel wireless flash memory with 3 volt i/o offers both hardware and software forms of data protection. software can individually lock and unlock any block for ? on-the-fly ? run-time data protection. for absolute data protection, all blocks are locked when the v pp voltage falls below the v pp lockout threshold. upon initial power up or return from reset, the 1.8 volt intel wireless flash memory with 3 volt i/o defaults to page mode. to enable burst mode, write and configure the configuration register. while in burst mode, the 1.8 volt intel wireless flash memory with 3 volt i/o is synchronized with the host cpu. additionally, a configurable wait signal can be used to provide easy flash-to- cpu synchronization. the 1.8 volt intel wireless flash memory with 3 volt i/o maintains compatibility with intel ? command user interface (cui), common flash interface (cfi), and intel ? flash data integrator (fdi) software tools. cui is used to control the flash device, cfi is used to obtain specific product information, and fdi is used for data management. the 1.8 volt intel wireless flash memory with 3 volt i/o and sram offers two low-power savings features: automatic power savings (aps) and standby mode. the flash device automatically enters aps following the completion of any read cycle. flash and sram standby modes are enabled when the appropriate chip select signals are de-asserted. finally, the 1.8 volt intel wireless flash memory with 3 volt i/o provides program and erase suspend/resume operations to allow system software to service higher priority tasks. it offers a 128-bit protection register that can be used for unique device identification and/or system security purposes. combined, all these features make the 1.8 volt intel wireless flash memory with 3 volt i/o and sram an ideal solution for any high-performance, low-power, board-constrained memory application.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 3 2.2 package diagram notes: 1. on lower density devices, upper address balls can be treated as no connects. for example, on a 32-mbit device, a 23-21 will be no connects. figure 1. 80-ball matrix, 0.80 mm ball pitch, stacked-csp for 32/4-, 64/8- and 128/tbd-mbit devices (flash + sram) 1 du a 4 a 18 a 19 s-v ss s- we# f-clk a 21 a 11 2 3 4 5 6 7 8 a 5 s-lb# a 23 s-v ss s-cs 2 s-v cc a 22 a 12 a 3 a 17 a 24 f-v pp f-v cc f-v ss a 9 a 13 a 2 a 7 a 25 f-wp# a 20 f-adv# a 10 a 15 a 1 a 6 s-ub# f-rst# f-we# a 8 a 14 a 16 a 0 dq 8 dq 2 dq 10 dq 5 dq 13 f-wait du s-oe# dq 0 dq 1 dq 3 dq 12 dq 14 dq 7 du s-cs 1 # f-oe# dq 9 dq 11 dq 4 dq 6 dq 15 du f-ce# du du s-v cc s-v cc du f-v ccq s-v ss s-v ss f-v ssq f-v ccq f-v cc s-v ss f-v ssq f-v ss s-v ss du 8 du a 11 a 21 f-clk s- we# s-v ss a 19 a 18 a 4 7 6 5 4 3 2 1 a 12 a 22 s-v cc s-cs 2 s-v ss a 23 s-lb# a 5 a 13 a 9 f-v ss f-v cc f-v pp a 24 a 17 a 3 a 15 a 10 f-adv# a 20 f-wp a 25 a 7 a 2 a 16 a 14 a 8 f-we# f-rst# s-ub# a 6 a 1 du f-wait dq 13 dq 5 dq 10 dq 2 dq 8 a 0 du dq 7 dq 14 dq 12 dq 3 dq 1 dq 0 s-oe# du dq 15 dq 6 dq 4 dq 11 dq 9 f-oe s-cs 1 # s-v ss f-v ccq du s-v cc s-v cc du du f-ce# s-v ss f-v ss f-v ssq s-v ss f-v cc f-v ccq f-v ssq s-v ss du top view - ball side down complete ink mark not shown bottom view - ball side up k a b c d e f g h j l m n p k a b c d e f g h j l m n p du du du du du du du du du du du du e d
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 4 preliminary note: 1. all balls will be populated; however, addresses a 21 and a 22 will be nc. figure 2. 56-ball matrix, 0.75 mm ball pitch, vf bga package and bga* package for the 32- mbit and 64-mbit discrete devices a b c d e f g a 11 a 8 v ss v cc v pp a 18 a 6 a 4 a 12 a 9 a 20 clk rst# a 17 a 5 a 3 a 13 a 10 adv# we# a 19 a 7 a 2 a 15 a 14 wait a 16 d 12 wp# a 1 v ccq d 15 d 6 d 4 d 2 d 1 ce# a 0 v ss d 14 d 13 d 11 d 10 d 9 d 0 oe# d 7 v ssq d 5 v cc d 3 v ccq d 8 v ssq a 4 a 6 a 18 v pp v cc v ss a 8 a 11 a 3 a 5 a 17 rst# clk a 20 a 9 a 12 a 2 a 7 we# adv# a 19 a 10 a 13 a 1 a 14 wp# d 12 a 16 wait a 15 a 0 ce# d 1 d 2 d 4 d 6 d 15 v ccq oe# d 0 d 9 d 10 d 11 d 13 d 14 v ss v ssq d 8 v ccq d 3 v cc d 5 v ssq d 7 a b c d e f g top view - ball side down complete ink mark not shown bottom view - ball side up 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 a 21 a 22 a 22 a 21 2.3 package dimensions table 1. package outline dimensions package type device density dimension-d ( 0.1 mm) dimension-e ( 0.1 mm) height (max.) (mm) vf bga 32 mbit 7.7 mm 9.0 mm 1.0 mm bga* 64 mbit 7.7 mm 9.0 mm 1.0 mm stacked-csp 32/4, 64/8 14.0 mm 8.0 mm 1.4 mm
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 5 2.4 signal descriptions table 2. signal descriptions (sheet 1 of 2) symbol type name and function a 25 ? 0 i address: device address. addresses are internally latched during read and write cycles. 32-mbit flash: a 20 ? 0 ; 64-mbit flash: a 21 ? 0 ; 128-mbit flash: a 22 ? 0 ; 4-mbit sram: a 17 ? 0 ; 8-mbit sram: a 18 ? 0 dq 15 ? 0 i/o data input/outputs: inputs data and commands during write cycles, outputs data during query, id reads, memory, status register, protection register, and configuration code reads. data signals float when the chip or outputs are deselected. data is internally latched during writes. query accesses and status register accesses use dq 0 ? dq 7 . all other accesses use dq 0 ? dq 15 . adv# i flash address valid: internally latches addresses. in page mode, addresses are internally latched on the rising edge of adv#. in burst mode, address internally latched on the rising edge of adv# or rising/ falling edge of clk, whichever occurs first. connect adv# to gnd when the flash device is operating in asynchronous mode only. ce# i flash chip enable: enables/disables flash device. ce#-low enables the device. ce#-high disables the device and places the device into standby mode. ce# high places data and wait signals at a high-z level. s-cs 1 #i sram chip select1: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs 1 # is active low. s-cs 1 # high deselects the sram memory device and reduces power consumption to standby levels. s-cs 2 i sram chip select2: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs 2 is active high. s-cs 2 low deselects the sram memory device and reduces power consumption to standby levels. clk i flash clock: synchronizes the device to the system bus frequency. (used only in burst mode.) oe# i flash output enable: enables/disables device output buffers. oe# low enables the device output buffers. oe# high disables the device output buffers and places all outputs at a high-z level. s-oe# i sram output enable: activates the sram outputs through the data buffers during a read operation. s-oe# is active low. rst# i flash reset: enables/disables device operation. rst# low initializes internal circuitry and disables device operation. rst# high enables device operation. wait o flash wait: indicates valid data in burst read mode. wait is at high-z until the configuration register bit cr.10 is set, which also determines its polarity when asserted. we# i flash write enable: enables/disables device write buffers. we# low enables the device write buffers. data is latched on the rising edge of we#. we# high disables the device write buffers. s-we# i sram write enable: controls writes to the sram memory array. s-we# is active low. s-ub# i sram upper byte enable: enables the upper bytes for sram (dq 15-8 ). s-ub# is active low. s-ub# and s-lb# must be tied together to restrict x16 mode. s-lb# i sram lower byte enable: enables the lower bytes for sram (dq 7-0 ). s-lb# is active low. s-ub# and s-lb# must be tied together to restrict x16 mode. wp# i flash write protect: enables/disables the device lock-down function. wp# low enables the lock- down mechanism and blocks marked lock-down cannot be unlocked by system software. wp# high disables the lock-down mechanism and blocks marked lock-down can be unlocked by system software. v pp pwr flash program/erase power: hardware erase and program protection. a valid v pp voltage on this ball allows erase or programming. memory contents cannot be altered when v pp < v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system read, program, and erase operations. v pp must remain above v pp1 min to perform in-system operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. v pp can be v pp2 for a cumulative total, not to exceed 80 hours maximum. extended use of this ball at v pp2 may reduce block cycling capability. v cc pwr flash power supply: flash operations at invalid v cc voltages should not be attempted. v ccq pwr flash output power supply: enables all input and output signals to be driven at v ccq .
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 6 preliminary note: for non-discrete devices, all flash signals are prefixed with f_ before its signal ? s name. 2.5 block diagram 2.6 flash memory map the 1.8 volt intel ? wireless flash memory with 3 volt i/o memory is divided into separate partitions to support the read-while-write/erase function. each partition is 4-mbits in size and can operate independently from other partitions. v ss pwr flash power supply ground: balls for internal device circuitry must be connected to system ground. v ssq pwr flash output power supply ground: balls for internal device circuitry must be connected to system ground. s-v cc pwr sram power supply: device operations at invalid s-v cc voltages should not be attempted. s-v ss pwr sram ground: balls for all internal device circuitry must be connected to system ground. du don ? t use: do not use this ball. this ball should not be connected to any power supplies, control signals and/or any other ball and must be floated. nc no connect: no internal connection. can be driven or floated. table 2. signal descriptions (sheet 2 of 2) symbol type name and function figure 3. 1.8 volt intel ? wireless flash memory with 3 volt i/o and slram block diagram 32, 64, 128 mbit flash memory ce# oe# we# rst# wp# v cc v ccq v pp 4 or 8 mbit sram s-sc 1 # s-sc 2 s-oe# s-we# s-lb# s-v cc s-v ss a 0-17 / a 0-18 a 18-20 / a 19-21 or a 19-22 dq 15-0 adv# clk wait v ss v ssq s-ub#
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 7 a 32-mbit device will have eight partitions; a 64-mbit device will have 16 partitions; a 128-mbit device will have 32 partitions. each main block is 32-kword in size. the 1.8 volt intel wireless flash memory with 3 volt i/o supports cpus that boot from either the top or bottom of the flash memory map. a top parameter flash device has the highest addressable 32-kword block divided into eight smaller blocks. conversely, a bottom parameter flash device has the lowest addressable 32-kword block divided into eight smaller blocks. each of these eight 4- kword blocks are called parameter blocks. parameter blocks are useful for frequently stored data variables. their smaller block size allows them to erase faster than main blocks. page- and burst- mode reads are also permitted in all blocks and across all partition boundaries. it should be mentioned that the sram does not adhere to this multi-partition architecture. the sram memory is organized as a single memory array.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 8 preliminary notes: 1. partition size: 4 mbit/256 kword/512 kbytes. 2. main block size: 32 kword/64 kbytes. 3. parameter block size: 4 kword/8 kbytes. 4. all partitions have 8 main blocks, except for top/bottom parameter partitions. 5. top/bottom parameter partitions have 15 blocks, 7 main and 8 parameter. figure 4. flash memory map . . . . . . partition 15 8 blocks start - stop addr 3f8000 - 3fffff 3f0000 - 3f7fff 3e8000 - 3e7fff 3e0000 - 3e7fff 3d8000 - 3d7fff 3d0000 - 3d7fff 3c8000 - 3cffff 3c0000 - 3c7fff 4 mbit partition 0 8 blocks start - stop addr 38000 - 3ffff 30000 - 37fff 28000 - 2ffff 20000 - 27fff 18000 - 1ffff 10000 - 17fff 08000 - 0ffff 00000 - 07fff 0 partition 7 8 blocks start - stop addr 1f8000 - 1fffff 1f0000 - 1f7fff 1e8000 - 1effff 1e0000 - 1e7fff 1d8000 - 1dffff 1d0000 - 1d7fff 1c8000 - 1cffff 1c0000 - 1c7fff partition 2 8 main blocks 80000 - bffff partition 1 8 main blocks 40000 - 7ffff 8 mbit partition 3 8 main blocks c0000 - fffff 12 mbit partition 4 8 main blocks 100000 - 13ffff 16 mbit 20 mbit partition 5 8 main blocks 140000 - 17ffff 24 mbit partition 6 8 main blocks 180000 - 1bffff 28 mbit 32 mbit 64 mbit 60 mbit partition 14 8 main blocks 380000 - 3bffff partition 1 8 main blocks 40000 - 7ffff 4 mbit 0 8 mbit partition 0 8 blocks start - stop addr 38000 - 3ffff 30000 - 37fff 28000 - 2ffff 20000 - 27fff 18000 - 1ffff 10000 - 17fff 08000 - 0ffff 00000 - 07fff xx8000 - xx8fff xx9000 - xx9fff xa000 - xxafff xxb000 - xxbfff xxc000 - xxcfff xxd000 - xxdfff xxe000 - xxefff xxf000 - xxffff 0000 - 0fff 1000 - 1fff 2000 - 2fff 3000 - 3fff 4000 - 4fff 5000 - 5fff 6000 - 6fff 7000 - 7fff bottom parameter device divides the lowest 32-kword main block into eight 4-kword parameter blocks top parameter device divides the highest 32-kword main block into eight 4-kword parameter blocks partition 31 8 blocks start - stop addr 7f8000 - 7fffff 7f0000 - 7f7fff 7e8000 - 7e7fff 7e0000 - 7e7fff 7d8000 - 7d7fff 7d0000 - 7d7fff 7c8000 - 7cffff 7c0000 - 7c7fff partition 30 8 main blocks 780000 - 7bffff . . . . . . partition 1 8 main blocks 40000 - 7ffff partition 0 8 blocks start - stop addr 38000 - 3ffff 30000 - 37fff 28000 - 2ffff 20000 - 27fff 18000 - 1ffff 10000 - 17fff 08000 - 0ffff 00000 - 07fff 4 mbit 8 mbit 128 mbit 124 mbit 8 main blocks start - stop addr f8000-fffff f0000-f7fff e8000-effff e0000-e7fff d8000-dffff d0000-d7fff c8000-cffff c0000-c7fff
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 9 3.0 product operations 3.1 bus operations the 1.8 volt intel ? wireless flash memory ? s on-chip write state machine (wsm) manages erase and program algorithms. the local cpu controls the in-system read, program, and erase operations of the flash device. bus cycles to and from the flash device conform to standard microprocessor bus operations. rst#, ce#, oe#, we#, and adv# signals control the flash. wait informs the cpu of valid data during burst reads. s-oe#, s-we#, s-cs 1 #, s-cs 2 , s-lb# and s-ub# control the sram. s-ub# and s-lb# must be tied together to restrict x16 mode. table 3 summarizes bus operations. notes: 1. manufacturer and device id codes are accessed by read id register command. 2. query and status register accesses use only dq 7-0 . all other accesses use dq 15-0 . 3. x must be v il or v ih for control signals and addresses. 4. refer to table 5, ? command bus definitions ? on page 11 for valid d in during a write operation. 5. two devices may not drive the memory bus at the same time. 6. the sram can be placed into data retention mode by lowering the s-v cc to the v dr limit when in standby mode. 7. always tie s-ub# and s-lb# together. 3.2 flash command definitions device operations are selected by writing specific commands to the command user interface (cui). table 4, ? command code and descriptions ? on page 10 lists all possible command codes and descriptions. table 5, ? command bus definitions ? on page 11 further defines command bus cycle operations. since commands are partition-specific, it is important to write commands within the target partition range. multi-cycle command writes to the flash memory partition must be issued sequentially without intervening command writes. for example, an erase setup command to partition x must be immediately followed by the erase confirm command in order to be executed properly. the address given during the erase confirm command determines the location of the erase. if the erase table 3. bus operations mode note rst# ce# oe# we# adv# wait s-cs 1 # s-cs 2 s-oe# s-we# s-ub# s-lb# 7 dq [15:0] flash read 1,2, 5 v ih v il v il v ih v il valid sram must be in high-z d out output disable 3 v ih v il v ih v ih x high-z any valid sram mode high-z standby 3 v ih v ih x x x high-z high-z reset 3 v il x x x x high-z high-z write 4, 5 v ih v il v ih v il v il high-z sram must be in high z d in sram read 5 flash must be in high-z high-z v il v ih v il v ih v il d out output disable 3 any valid flash mode v il v ih v ih v ih x high-z standby and data retention 3, 6 v ih xxx xhigh-z xv il x x x high-z write 5 flash must be in high-z high-z v il v ih v ih v il v il d in
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 10 preliminary confirm command is given to partition x, then the command will be executed, and a block in partition x will be erased. alternatively, if the erase confirm command is given to partition y, the command will still be executed, and a block in partition y will be erased. any other command given to any partition prior to the erase confirm command will result in a command sequence error, which is posted in the status register. after the erase has successfully started in partition x or y, read cycles can occur in any other partition. table 4. command code and descriptions (sheet 1 of 2) mode instruction code command description read ffh read array places addressed partition in read array mode. 70h read status register places addressed partition in read status register mode. a partition automatically enters the read status register mode after a valid program/erase command is executed. 90h read id register, read configuration register puts the addressed partition in read device identifier mode. the device outputs manufacturer and device id codes, configuration register settings, block lock status and protection register data. data is output on dq 15-0 . 98h read query register puts the addressed partition in read query mode. the device outputs common flash interface (cfi) information on dq 7-0 . 50h clear status register clears status register bits 1, 3, 4 and 5. the wsm can set (1) and reset (0) bits 0, 2, 6 and 7. program 40h word program setup the preferred first bus cycle program command that prepares the wsm for a program operation. the second bus cycle command latches the address and data. a read array command is required to read array data after programming. 10h alternate word program setup equivalent to a word program setup command (40h). 30h enhanced factory programming setup activates enhanced factory programming mode (efp). the first bus cycle sets up the command. if the second bus cycle is a confirm command (d0h), subsequent writes provide program data. all other commands are ignored once efp mode begins. d0h enhanced factory programming confirm if the first command was enhanced factory programming setup (30h), the cui latches the address, confirms command data, and prepares the device for efp mode. erase 20h block erase setup prepares the wsm for a block erase operation. the device erases the block addressed by the erase confirm command. if the next command is not erase confirm, the cui (a) sets status register bits sr.4 and sr.5 to ? 1, ? (b) places the partition in the read status register mode (c) waits for another command. d0h erase confirm if the first command was erase setup (20h), the wsm latches address and data and erases the block indicated by the erase confirm cycle address. during program/erase, the partition responds only to read status register, program suspend, and erase suspend commands. ce# or oe# toggle updates status register data. suspend b0h program or erase suspend this command issued at any device address initiates suspension of the currently executing program/erase operation. the status register, invoked by a read status register command, indicates successful operation suspension by setting (1) status bits sr.2 (program suspend) or sr.6 (erase suspend) and sr.7. the wsm remains in the suspend mode regardless of control signal states, except rst# = v il . d0h suspend resume this command issued at any device address resumes suspended program or erase operation. block locking 60h lock setup prepares the wsm lock configuration. if the next command is not block-lock, unlock, or lock-down the wsm sets sr.4 and sr.5 to indicate command sequence error. 01h lock block if the previous command was lock setup (60h), the cui locks the addressed block. d0h unlock block after a lock setup (60h) command the cui latches the address and unlocks the addressed block. if previously locked-down, the operation has no effect. 2fh lock-down after a lock setup (60h) command, the cui latches the address and locks-down the addressed block.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 11 note: unassigned instruction codes should not be used. intel reserves the right to redefine these codes for future functions. notes: 1. first cycle command addresses should be the same as the operation ? s target address. examples: the first- cycle address for the read id register command should be the same as the identification code address (ia); the first cycle address for the program command should be the same as the word address (wa) to be programmed; the first cycle address for the erase/program suspend command should be the same as the address within the block to be suspended; etc. xx = any valid address within the device. ia = identification code address. ba = address within the block. lpa = lock protection address is obtained from the cfi (via the read query command). intel ? 1.8 volt protection c0h protection program setup prepares the wsm for a protection register program operation. the second bus cycle latches address and data. to read array data after programming, issue a read array command. configuration 60h configuration setup prepares the wsm for device configuration. if set configuration register is not the next command, the wsm sets sr.4 and sr.5 to indicate command sequence error. 03h set configuration register if the previous command was configuration setup (60h), the wsm writes data into the configuration register via a 15-0 . following a set configuration register command, subsequent read operations access array data. table 4. command code and descriptions (sheet 2 of 2) mode instruction code command description table 5. command bus definitions mode command bus cycles first bus cycle second bus cycle oper addr (1) data (2,3) oper addr (1) data (2,3) read read array 1 write pna ffh read id register 2 write xna 90h read xna+ia ic read query register 2 write pna 98h read pna+qa qd read status register 2 write pna 70h read ba srd clear status register 1 write xx 50h program erase block erase 2 write ba 20h write ba d0h word program 2 write wa 40h/10h write wa wd enhanced factory program > 2 write wa 30h write wa d0h program/erase suspend 1 write xx b0h program/erase resume 1 write xx d0h lock lock block 2 write ba 60h write ba 01h unlock block 2 write ba 60h write ba d0h lock-down block 2 write ba 60h write ba 2fh protec- tion protection program 2 write pa c0h write pa pd lock protection program 2 write lpa c0h write lpa fffdh config- uration set configuration register 2 write cd 60h write cd 03h
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 12 preliminary wireless flash memory flash memory family ? s lpa is at 0080h. pa = user programmable 4-word protection address in the device identification plane. pna = address within the partition. xna = base address where x can be partition, main block or parameter block. see figure 11, ? device identification codes ? on page 21 for details. qa = query code address. wa = word address of memory location to be written. 2. srd = data read from the status register on dq 7-0. wd = data to be written at location wa. ic = identifier code data. pd =user programmable 4-word protection data. qd = query code data on dq 7-0 . cd = configuration register code data presented on device addresses a 15 ? 0 . a max-16 address bits can select any partition . see table 6, ? configuration register bits ? on page 13 for configuration register bits descriptions. 3. commands other than those shown above are reserved by intel for future device implementations and should not be used. . 4.0 flash read modes 4.1 read array 4.1.1 asynchronous mode the 1.8 volt intel ? wireless flash memory with 3 volt i/o supports asynchronous reads. an asynchronous read is executed by implementing a read operation without the use of the clk signal. during an asynchronous read operation, the clk signal is ignored. if asynchronous reads will be the only read mode of operation, it is recommended that the clk signal be held at a valid v ih level. page mode is the default read mode after power-up or reset. a page-mode read outputs 4 words of asynchronous data; however, by manipulating certain control signals, the device can be made to output less than 4 words. after power-up or reset, it is not necessary to execute the read array command before accessing the flash memory. however, to perform a flash read at any other time, it is necessary to execute the read array command before accessing the flash memory. page mode is permitted in all blocks, across all partition boundaries and operates independent of v pp . a single-word read can be used to access register information. during asynchronous reads, the address is latched on the rising edge of adv#. upon completion of reading the array, the device automatically enters an automatic power savings (aps) mode. aps mode consumes power comparable to standby mode. 4.1.2 synchronous mode the 1.8 volt intel ? wireless flash memory supports synchronous reads. a synchronous read is executed by implementing a read operation with the use of the clk signal. during a synchronous read operation, the clk signal edge (rising or falling) controls flash array access. a burst-mode read is synchronized to the clk signal and outputs a 4-, 8- or continuous-word data stream based on configuration register settings. however, by manipulating certain control signals, the device can be made to output less then 4-, 8- or continuous-words.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 13 burst mode is not the default mode after power-up or a device reset. to perform a burst-mode read, the configuration register must be set. to set the configuration register, refer to section 4.2, ? set configuration register (cr) ? on page 13 . after setting the configuration register, if the first device operation is a burst-mode read, it is not necessary to execute the read array command before accessing the flash memory. however, to perform a flash read at any other time, it is necessary to execute the read array command before accessing the flash memory array. burst mode is permitted in all blocks, across all partition boundaries and operates independently of v pp. a single-word burst-mode read cannot be used to access register information. in burst mode, the address is latched by either the rising edge of adv# or the rising edge of clk with adv# low, whichever occurs first. upon completion of reading the array, the device automatically enters an automatic power savings (aps) mode. aps mode consumes power comparable to standby mode. 4.2 set configuration register (cr) the configuration register is 16 bits wide. this register is used to configure the burst mode parameters. therefore, if using page mode, it is not necessary to set this register. to set the configuration register, execute the set configuration register command. the 16 bits of data used by this command must be placed on address lines a 15 ? 0 . all other address lines must be held low (v il ). after setting the configuration register, if the first device operation is a flash burst-mode read, it is not necessary to execute the read array command before accessing the flash memory. however, to perform a burst-mode read at any other time, it is necessary to execute the read array command before accessing the flash memory. notes: 1. ? r ? bits are reserved bits. these bits and all other address lines must be set low. 2. on power-up or return from reset, all bits are set to ? 1. ? table 6. configuration register bits configuration register bits 2 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 rm r 1 lc 2-0 wt doc wc bs cc r 1 r 1 bw bl 2-0 000
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 14 preliminary . 4.2.1 read mode (rm) cr.15 sets the flash read mode. the two read modes are page mode (default mode) and burst mode. the flash device can only be configured for one of these modes at any one time. 4.2.2 first latency count (lc 2 ? 0 ) the first access latency count configuration tells the device how many clocks must elapse from adv#-high (v ih ) before the first data word should be driven onto its data pins. the input clock frequency determines this value. see table 6, ? configuration register bits ? on page 13 for latency values. figure 7, ? first access latency configuration ? on page 16 shows data output latency from adv#-active for different latencies. use these equations to calculate first access latency count: {1/ frequency} = clk period (1) n (clk period) t avqv (ns) + t add-delay (ns) + t data (ns) (2) n-2 = first access latency count (lc) * (3) table 7. configuration register bit settings bit name setting read mode (rm) cr.15 0 = burst or synchronous mode. 1 = page or asynchronous mode. first latency count (lc 2-0 ) cr.13 ? cr.11 code 0 = 000. reserved. code 1 = 001. reserved. code 2 = 010. code 3 = 011. code 4 = 100. code 5 = 101. code 6 = 110. reserved. code 7 = 111. reserved. wait polarity (wt) cr.10 0 = active low signal. 1 = active high signal data output configuration (doc) cr.9 0 = hold data for one clock cycle. 1 = hold data for two clock cycles. wait configuration (wc) cr.8 0 = wait signal asserted during 16-word row boundary transition. 1 = wait signal assert one data cycle before 16-word row boundary transition. burst sequence (bs) cr.7 0 = intel burst sequence. 1 = linear burst sequence. clock configuration (cc) cr.6 0 = falling edge of clock. 1 = rising edge of clock. burst wrap (bw) cr.3 0 = wrap enabled. 1 = wrap disabled. burst length (bl 2-0 ) cr.2 ? cr.0 001 = 4 word burst mode. 010 = 8 word burst mode. 011 = reserved. 111 = continuous burst mode.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 15 n: # of clock periods (rounded up to the next integer) * must use lc = n - 1 when the starting address is not aligned to a four-word boundary and cr.3 = 1 (no wrap). note: 1. the 16-word boundary is the end of device word-line. parameters defined by cpu : t add-delay = clock to ce#, adv#, or address valid whichever occurs last. t data = data set up to clock. parameters defined by flash : t avqv = address to output delay. example : cpu clock speed = 52 mhz t add-delay = 6 ns (typical speed from cpu) (max) t data = 4 ns (typical speed from cpu) (min) t avqv = 70 ns (from ac characteristic - read only operations table) from eq. (1): 1/52 (mhz) = 19.2 ns from eq. (2) n(19.2 ns) 70 ns + 6 ns + 4 ns n(19.2 ns) 80 ns n 80/19.2 = 4.17 = 5 (integer) from eq. (3) n - 2 = 5 - 2 = 3 first access latency count setting to the cr is code 3. ( figure 6, ? data output with lc setting at code 3 ? on page 16 displays example data) table 8. first latency count (lc) lc setting mode wrap aligned to 4-word boundary wait asserted on 16-word boundary crossing n-1 4 or 8 disabled no yes, occurs on every occurrence n-2 4 or 8 disabled yes no n-2 4 or 8 enabled no no n-2 4 or 8 enabled yes no n-1 continuous x x yes, occurs once figure 5. word boundary 0123456789abcdef 16 word boundary word 0 - 3 word 4 - 7 word 8 - b word c - f 4 word boundary
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 16 preliminary the formula t avqv (ns) + t add-delay (ns) + t data (ns) is also known as initial access time. figure 6 shows the data output available and valid after four clocks from adv# going low in the first clock period with the lc setting at 3. 4.2.3 wait signal polarity (wt) the wait signal polarity is set by register bit cr.10 (wt). when cr.10 = 0, wait is active low. a ? 0 ? on the wait signal indicates the ? asserted ? state. figure 6. data output with lc setting at code 3 figure 7. first access latency configuration a max-0 dq 15-0 (d/q) clk (c) ce# adv# r103 valid output valid output high z t add t data 2nd 1st 3rd 4th 5th valid address code 3 code 1 (reserved) code 6 (reserved) code 5 code 4 code 3 code 2 code 0 (reserved) code 7 (reserved) valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] dq 15-0 [d/q] clk [c] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] freqconf.wmf
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 17 when cr.10 = 1, wait is active high. a ? 1 ? on the wait signal indicates the ? asserted ? state. wa it s ign a l ? asserted ? means that the wait signal is indicating a ? wait ? condition. wa it s ign a l ? deasserted ? means that the wait signal is not indicating a ? wait ? condition (i.e., the bus is valid). wait is high-z until the device is active (ce# = v il ). in synchronous read array mode, when the device is active (ce# = v il ) and data is valid, cr.10 (wt) determines if wait goes to v oh or v ol. the wait signal is only ? deasserted ? when data is valid on the bus. invalid data drives the wa it si gn a l to ? asserted ? state. in asynchronous page mode, wait is always set to an ? asserted ? state (cr.10 = 1) 4.2.4 wait signal function the wait signal indicates data valid when the device is operating in synchronous burst mode (cr.15 is set to ? 0 ? ), and when addressing a partition that is currently in read array mode. the wait signal is only ? deasserted ? when data is valid on the bus. the wait signal polarity is set by cr.10. when the device is operating in synchronous non-read-array mode, such as read status, read id, or read query, wait is set to an ? asserted ? state as determined by cr.10. figure 20 on page 46 displays wait signal in synchronous non-read array operation waveform. when the device is operating in asynchronous page mode or asynchronous single word read mode, wait is set to an ? asserted ? state as determined by cr.10. see figure 21, ? wa i t s i g n a l i n asynchronous page-mode read operation waveform ? on page 47 and figure 22, ? wa i t s i g n a l i n asynchronous single-word read operation waveform ? on page 48 . from a system perspective, the wait signal will be in the asserted state (based on cr.10) when the device is operating in synchronous non-read array mode (such as read id, read query, or read status), or if the device is operating in asynchronous mode (cr.15 is set to ? 1 ? ). in these cases, the system software should ignore (mask) the wait signal, as it does not convey any useful information about the validity of what is appearing on the data bus. systems may tie several components ? wait signals together. 4.2.5 data output configuration (doc) the data output configuration bit (cr.9) determines whether a data word remains valid on the data bus for one or two clock cycles. the processor ? s minimum data set-up time and the flash memory ? s clock-to-data output delay determine whether one or two clocks are needed. if the data output configuration is set at one-clock data hold, this corresponds to a one-clock data cycle; if the data output configuration is set at two-clock data hold, this corresponds to a two- clock data cycle. this configuration bit ? s setting depends on the system and cpu characteristics. refer to figure 8, ? data output configuration with wait signal delay ? on page 18 for clarification. a method for determining what this configuration should be set at is shown below: to set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns)
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 18 preliminary as an example, a clock frequency of 52 mhz will be used. the clock period is 19.2 ns. this data is applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 14 ns + 4 ns 19.2 ns this equation is satisfied and data output will be available and valid at every clock period. if t data is long, hold for two cycles. now assume the clock frequency is 66 mhz. this corresponds to a 15 ns period. the initial access time is calculated to be 80 ns (lc 4). this condition satisfies t avqv (ns) + t add-delay (ns) + t data (ns) = 70 ns + 6 ns + 4 ns = 80 ns, as shown above in the first access latency count equations. however, the data output hold time of one clock violates the one-clock data hold condition: t chqv (ns) + t data (ns) one clk period 14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. to satisfy the formula above, the data output hold time must be set at 2 clocks to correctly allow for data output setup time. this formula is also satisfied if the cpu has t data (ns) 1 ns, which yields: 14 ns + 1 ns 15 ns in page mode reads, the initial access time can be determined by the formula: t add-delay (ns) + t data (ns) + t avqv (ns) and subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) 4.2.6 wait configuration (wc) cr.8 sets the wait signal delay. the wait signal delay determines when the wait signal is asserted. the wait signal can be asserted either one clock before or at the time of the misaligned 16-word boundary crossing. an asserted wait signal indicates invalid data on the data bus. figure 8. data output configuration with wait signal delay dq 15-0 [q] clk [c] valid output valid output valid output dq 15-0 [q] valid output valid output 1 clk data hold wait (cr.8 = 1) wait (cr.8 = 0) t chqv t chqv wait (cr.8 = 0) wait (cr.8 = 1) 2 clk data hold t chtl/h note 1 note 1 note 1 note 1 note1: wait shown active high (cr.10 = 1)
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 19 in synchronous mode, wait is active when ce# is asserted. the wait signal is asserted if a burst-mode read is misaligned to a 4-word boundary. by misaligned, we imply that the address must be on a mod-4 boundary; such as xx00h, xx04h, xx08h or xx0ch. if the address is aligned to a 4-word boundary, the ? delay ? will never be seen. also, a ? delay ? will only occur once per burst- mode read sequence. when a misaligned burst-mode read crosses a 16-word boundary, the device must deselect one row in order to select the next row. it is this selecting/de-selecting (or energizing/ de-energizing) of memory rows that causes the device to ? delay ? output data. it is the assertion of the wait signal that informs the interfacing processor of this pending flash ? delay. ? during the ? delay, ? subsequent data reads are prohibited. the wait signal is asserted depending on the burst starting address and latency count. if the starting address is aligned to the 4-word boundary, a delay will not occur. if the starting address is aligned to the end of a 4-word boundary, a delay equal to one clock cycle less than the latency count will occur (worst case scenario). see table 9, ? wa i t d e l a y ? on page 19 . if the starting address falls between, the delay will be dependent upon the latency count value and the starting address as indicated in table 9 . in 4- and 8-word burst modes with burst wrap enabled, the device will not assert the wait signal. however, with the burst wrap disabled, the flash device will assert the wait signal if a burst-mode read is misaligned and crosses a 16-word boundary. with wrap disabled, the burst mode will read 4 or 8 consecutive words based on the initial address. if the initial address is aligned on a mod-4 boundary, the wait signal will not be asserted. however, if the initial address is misaligned on a mod-4 boundary and crosses the 16-word boundary limit, the wait signal will be asserted. in continuous-word burst mode, the burst wrap feature does not apply and the wait signal is only asserted on the first 16-word boundary crossing. the wait signal is inactive or at a high-z state when accessing register information. table 9. wait delay 4.2.7 burst sequence (bs) cr.7 sets the burst sequence. the burst sequence determines the 4- or 8-word output order. in 4- or 8-word burst modes, the burst sequence is defined as either linear or intel. in continuous burst mode, the burst sequence is always linear. the burst sequence depends on the interfacing processor ? s characteristics. starting burst address wait delay in clock cycles after crossing 16-word boundary 4-word boundary xx0h, xx4h, xx8h, xxch no delay start of boundary xx1h, xx5h, xx9h, xxdh lc - 3 xx2h, xx6h, xxah, xxeh lc - 2 xx3h, xx7h, xxbh, xxfh lc - 1 end of boundary
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 20 preliminary 4.2.8 clock configuration (cc) cr.6 sets the clock configuration. the clock configuration determines which edge of the clock the flash device will respond to while in burst mode. the device can be configured to either track on the rising or falling edge of the clock. table 10. sequence and burst length start addr (decimal) wrap (cr.3) burst addressing sequence (decimal) 4-word burst length (cr 2-0 = 001) 8-word burst length (cr 2-0 = 010) continuous burst (cr 2-0 = 111) linear intel linear intel linear 0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-... 1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-... 2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-... 3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-... 40 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-... 50 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-... 60 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-... 70 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-... ... ... ... ... ... ... ... 14 0 14-15-16-17-18-19-20- ... 15 0 15-16-17-18-19-20-21- ... ... ... ... ... ... ... ... 0 1 0-1-2-3 na 0-1-2-3-4-5-6-7 na 0-1-2-3-4-5-6-... 1 1 1-2-3-4 na 1-2-3-4-5-6-7-8 na 1-2-3-4-5-6-7-... 2 1 2-3-4-5 na 2-3-4-5-6-7-8-9 na 2-3-4-5-6-7-8-... 3 1 3-4-5-6 na 3-4-5-6-7-8-9-10 na 3-4-5-6-7-8-9-... 41 4-5-6-7-8-9-10-11 na 4-5-6-7-8-9-10-... 51 5-6-7-8-9-10-11-12 na 5-6-7-8-9-10-11-... 61 6-7-8-9-10-11-12-13 na 6-7-8-9-10-11-12-... 71 7-8-9-10-11-12-13- 14 na 7-8-9-10-11-12-13-... ... ... ... ... ... ... ... 14 1 14-15-16-17-18-19-20- ... 15 1 15-16-17-18-19-20-21- ...
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 21 4.2.9 burst wrap (bw) cr.3 sets the burst wrap. the burst wrap determines how the device will handle a burst-mode read that crosses a 16-word row boundary. wrap can be set to have either the burst mode wrap around to the same row or have the burst read consecutive addresses. wrap applies to 4- and 8-word burst modes only. wrap has no effect in continuous burst mode. in 4- and 8-word burst mode with wrap enabled, the wait signal will not be asserted. in 4- and 8- word burst mode with wrap disabled, the wait signal will be asserted only if a 16-word row boundary is crossed. 4.2.10 burst length (bl 2 ? 0 ) cr.2 ? cr.0 sets the burst length. the burst length determines the maximum number of consecutive words the device will output during a burst-mode read. 1.8 volt intel ? wireless flash memory with 3 volt i/o supports 4-, 8- and continuous-word burst lengths. 4.3 read query register the query plane comes to the foreground and occupies a 4-mbit address range at the partition supplied by the read query command address. the mode outputs common flash interface (cfi) data when partition addresses are read. appendix c, ? common flash interface ? on page 68 shows query mode information and addresses. issuing a read query command to a partition that is programming or erasing places that partition ? s outputs in read query mode while the partition continues to program or erase in the background. the read query command is subject to read restrictions dependent on the parameter partition availability. refer to table 15, ? simultaneous operations allowed with the protection register ? on page 32 for details. 4.4 read id register the identification (id) register contains various product information, such as manufacturer id, device id, block lock status, protection register information, and configuration register settings. to obtain any information from the id register, execute the read id register command. information contained in this register can only be accessed by executing a single-word asynchronous read. table 11. device identification codes item address (1,2,3) data manufacturer code pba + 000000h 0089h device code: 32 mbit - t pba + 000001h 8852h - b 8853h 64 mbit - t pba + 000001h 8854h - b 8855h 128 mbit - t pba + 000001h 8856h - b 8857h block lock configuration (4) mbba + 000002h or pbba + 000002h, depends on block ? block is unlocked dq 0 = 0 ? block is locked dq 0 = 1 ? block is not locked-down dq 1 = 0 ? block is locked-down dq 1 = 1
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 22 preliminary notes: 1. pba = partition base address. pba = a max - 18 . 2. mbba = main block base address. mbba = a max - 15 . 3. pbba = parameter block base address. pbba = a max - 12 . 4. see the block lock status section for valid lock status. 5. cd = configuration register settings. 6. pr-lk = protection register lock status. 7. pr = protection register data. 4.5 read status register the status register is 8 bits wide. the status register contains information pertaining to the current condition of the flash device and its partitions. to determine a partition ? s status, execute the read status register command. to read status register data, execute a signal-word asynchronous read. a status register bit is considered set if its value is a one (1) and cleared if its value is a zero (0). status register data is output on dq 7 ? 0 ; dq 15 ? 8 outputs 00h. each partition has its own status register data. information contained in this register can only be accessed by executing a single- word asynchronous read. configuration register settings pba + 000005h cd (5) protection register lock status pba + 000080h pr-lk (6) protection register data pba +000081h - 000088h pr (7) table 11. device identification codes item address (1,2,3) data
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 23 table 12. status register definitions dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 dws ess es ps vpps pss dps pws sr.7 sr.6 sr.5 sr.4 sr.3 sr.2 sr.1 sr.0 sr bit bit name notes sr.7 device wsm status (dws) 0 = device busy with a program or erase operation. 1 = device ready. for efp, see table 13 . sr.6 erase suspend status (ess) 0 = no erase operation, if any, is being suspended. 1 = an erase operation is being suspended. sr.5 erase suspend (es) 0 = block erase successful. 1 = block erase error. one of three bits set to indicate a command sequence error. sr.4 program status (ps) 0 = word program successful. 1 = word program error. one of three bits set to indicate a command sequence error. sr.3 v pp status (vpps) 0 = v pp voltage level > v pplk . 1 = v pp voltage level < v pplk . hardware program/erase lockout. note: this bit does not provide continuous v pp feedback. signal functionality is not guaranteed when v pp v pp1 or v pp2 . sr.2 program suspend status (pss) 0 = no program operation, if any, is being suspended. 1 = a program operation is being suspended. sr.1 device protect status (dps) 0 = block unlocked. 1 = an erase or program operation was attempted on a locked block. wp# = v il . sr.0 partition write/erase status (pws) 0 = no other partition is busy. 1 = another partition is busy performing an erase or program operation. for efp, see table 13 . table 13. status register dws and pws description dws (sr.7) pws (sr.0) description 00 the addressed partition is performing a program/erase operation. no other partition is active. enhanced factory programming: device is finished programming or verifying data or is ready for data. 01 a partition other than the one currently addressed is performing a program/erase operation. enhanced factory programming: the device is either programming or verifying data. 10 no program/erase operation is in progress in any partition. erase and program suspend bits (sr.6 and sr.2) indicate whether other partitions are suspended. enhanced factory programming: the device has exited efp mode. 11 won ? t occur in standard program or erase modes. enhanced factory programming: this combination will not occur.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 24 preliminary 4.5.1 clear status register to clear the status register, execute the clear status register command. when the status register is cleared, only bits 1, 3, 4, and 5 are cleared. a status register bit is considered set if its value is a one (1) and cleared if its value is a zero (0). since bits 0, 2, 6 and 7 indicated different error conditions and/or device states, these bits can only be set and cleared by the wsm and are not cleared when a clear status register command is given. the status register should be cleared before implementing any program or erase operations. after executing the clear status register command, the device returns to read array mode. a device reset also clears the status register. 4.6 read-while-write/erase 1.8 volt intel ? wireless flash memory supports a new flash multi-partition architecture. by dividing the flash memory into many separate partitions, the device is capable of reading from one partition while programing or erasing in another partition; hence the terms, read-while-write (rww) and read-while-erase (rwe). these features greatly enhance flash data storage performance. to perform a rww operation, execute the word program command to one partition. while this operation is being performed by the flash wsm, execute the read array command to another partition. to perform a rwe operation, execute the block erase command to one partition. while this operation is being performed by the flash wsm, execute the read array command to another partition. 1.8 volt intel wireless flash memory does not support simultaneous program and erase operations. attempting to perform operations such as these will result in a command sequence error. only one partition may be programming or erasing while another is reading. 5.0 program and erase voltages the 1.8 volt intel ? wireless flash memory with 3 volt i/o and sram memory provides in- system program and erase at v pp1 . for factory programming, it also includes a low-cost, backward-compatible 12 v programming feature. it also includes an enhanced factory programming (efp) feature. 5.1 factory program mode the standard factory programming mode uses the same commands and algorithm as the word program mode (40h/10h). when v pp is at v pp1 , program and erase currents are drawn through the v cc pin. note that if v pp is driven by a logic signal, v pp1 must remain above the v pp1 min value to perform in-system flash modifications. when v pp is connected to a 12 v power supply, the device draws program and erase current directly from the v pp pin. this eliminates the need for an external switching transistor to control the v pp voltage. figure 9, ? example of v pp power supply configurations shows examples of flash power supply usage in various configurations.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 25 the 12 v v pp mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during program and erase operations as specified in section 11.2, ? extended temperature operation ? on page 35 . v pp may be connected to 12 v for a total of t pph hours maximum. stressing the device beyond these limits may cause permanent damage. 5.2 programming voltage protection (v pp ) in addition to the flexible block locking, holding the v pp programming voltage low can provide absolute hardware write protection of all flash-device blocks. if v pp is below v pplk , program or erase operations will result in an error displayed in the status register bit sr.3 (set to 1). note: if the v cc supply can sink adequate current, an appropriately valued resistor can be used. 5.3 enhanced factory programming (efp) efp substantially improves device programming performance via a number of enhancements to the conventional 12-volt word program algorithm. efp's more efficient wsm algorithm eliminates the traditional overhead delays of conventional word program mode in both the host programming system and the flash device. changes to the flowchart and internal routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was struck. after a single command sequence, host programmer bus cycles write data words followed by status checks to determine when the next data word is ready to be accepted. this modification essentially cuts write bus cycles in half. following each internal program pulse, the wsm automatically increments the device's address to the next physical location. now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. in combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. additionally, efp speeds up programming by performing internal code verification. with this, prom programmers can rely on the device to verify that it's been programmed properly. from the device side, efp streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. figure 9. example of v pp power supply configurations ? 12 v fast programming ? absolute write protection with v pp v pplk system supply (note 1) v cc v pp 12 v supply v cc v pp ? low voltage and 12 v fast programming system supply 12 v supply ? low-voltage programming ? absolute write protection via logic signal system supply v cc v pp prot# (logic signal) ? low-voltage programming system supply v cc v pp 10k ?
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 26 preliminary efp consists of four phases: setup, program, verify and exit. refer to figure 32, ? enhanced factory program flowchart ? on page 63 for a detailed graphical representation on how to implement efp. 5.3.1 efp requirements and considerations efp requirements: ambient temperature: t a = 25 c 5 c v cc within specified operating range v pp within specified v pp2 range target block unlocked efp considerations: block cycling below 10 erase cycles (1) rww not supported (2) efp programs one block at a time efp cannot be suspended (1) recommended for optimum performance. some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. (2) code or data cannot be read from another partition during efp. 5.3.2 setup phase after receiving the efp setup (30h) and confirm (d0h) command sequence, device sr.7 transitions from a ? 1 ? to a ? 0 ? indicating that the wsm is busy with efp algorithm startup. a delay before checking sr.7 is required to allow the wsm time to perform all of its setups and checks (v pp level and block lock status). if an error is detected, status register bits sr.4, sr.3 and/or sr.1 are set and efp operation terminates. 5.3.3 program phase after setup completion, the host programming system must check sr.0 to determine ? data-stream ready ? status (sr.0=0). each subsequent write after this is a program-data write to the flash array. each cell within the memory word to be programmed to ? 0 ? will receive one wsm pulse; additional pulses, if required, occur in the verify phase. sr.0=1 indicates that the wsm is busy applying the program pulse. the host programmer must poll the device's status register for the ? program done ? state after each data-stream write. sr.0=0 indicates that the appropriate cell(s) within the accessed memory location have received their single wsm program pulse, and that the device is now ready for the next word. although the host may check full status for errors at any time, it is only necessary on a block basis, after efp exit. addresses must remain within the target block. supplying an address outside the target block immediately terminates the program phase; the wsm then enters the efp verify phase.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 27 the address can either hold constant or it can increment. the device compares the incoming address to that stored from the setup phase (wa 0 ); if they match, the wsm programs the new data word at the next sequential memory location. if they differ, the wsm jumps to the new address location. the program phase concludes when the host programming system writes to a different block address; data supplied must be ffffh. upon program phase completion, the device enters the efp verify phase. 5.3.4 verify phase a high percentage of the flash bits program on the first wsm pulse. however, for those cells that do not completely program on their first attempt, efp internal verification identifies them and applies additional pulses as required. the verify phase is identical in flow to that of the program phase, except that instead of programming incoming data, the wsm compares the verify-stream data to that which was previously programmed into the block. if the data compares correctly, the host programmer proceeds to the next word. if not, the host waits while the wsm applies an additional pulse(s). the host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. it then reissues each data word in the same order it did during the program phase. like programming, the host may write each subsequent data word to wa 0 or it may increment up through the block addresses. the verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be ffffh. upon verify phase completion, the device enters the efp exit phase. 5.3.5 exit phase sr.7=1 indicates that the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. after efp exit, any valid cui command can be issued. 5.4 write protection (v pp < v pplk ) if the v pp voltage is below the v pp lockout threshold, word programming is prohibited. to ensure proper word program operation, v pp must be set to one of the two valid v pp ranges. to determine program status, poll the status register and analyze the bits. when v pp is at v pp1 , program currents are drawn through the v cc supply. if v pp is driven by a logic signal, v pp1 must remain above the v pp1 minimum value in order to program erase mode. 6.0 flash erase mode 6.1 block erase flash erasing is performed on a block-by-block basis; therefore, only one block may be erased at any given time. once a block is erased, all bits within that block will read as a logic level one (1).
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 28 preliminary to erase a block, execute the block erase command. to determine the status of a block erase, poll the status register and analyze the bits. if the device is put in standby mode during an erase operation, the device will continue to erase until to operation is complete; then it will enter standby mode. refer to figure 33, ? block erase flowchart ? on page 64 for a detailed flow on how to implement a block erase operation. 6.2 erase protection (v pp < v pplk ) if the v pp voltage is below the v pp lockout threshold voltage, block erasure is prohibited. to ensure proper block erase operation, v pp must be set to one of the two valid v pp levels. to determine block erase status, poll the status register and analyze the bits. when v pp is at v pp1 , erase currents are drawn through the v cc supply. if v pp is driven by a logic signal, v pp1 must remain above the v pp1 minimum value in order to erase a block. 7.0 flash suspend/resume modes 7.1 program/erase suspend to suspend program or erase, execute the suspend command. suspend halts any in - progress word programming or block erase operation. the suspend command can be written to any device address, and the partition being addressed remains in its previous command state. a suspend command allows data to be accessed from any memory location other than those suspended. a program operation can be suspended to allow a read. an erase operation can be suspended to allow word programming or device reads within any except the suspended block. a program operation nested within an erase suspend can be suspended to read the flash device. once the program/erase process starts, a suspend can only occur at certain points in the program/erase algorithm. erase cannot resume until program operations initiated during the erase suspend are complete. all device read functions are permitted during suspend. during a suspend, v pp must remain at a valid program level and wp# must not change. also, a minimum time is required between issuing a program or erase command and then issuing a suspend command. 7.2 program/erase resume the resume command (d0h) instructs the wsm to continue programming/erasing and automatically clears status register bits sr.2 (or sr.6) and sr.7. the resume command can be written to any partition. if status register error bits are set, the status register can be cleared before issuing the next instruction. rst# must remain at v ih . see figure 31, ? program suspend/resume flowchart ? on page 62 and figure 34, ? erase suspend/resume flowchart ? on page 65 . if a suspended partition was placed in read array, read status register, read identifier (id), or read query mode during the suspend, the device will remain in that mode and output data corresponding to that mode after the program or erase operation is resumed. after resuming a suspend operation,
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 29 always issue the read mode command appropriate to the read operation. to read status after resuming a suspended operation, issue a read status register command (70h) to return the suspended partition to status mode. 8.0 flash security modes the 1.8 volt intel ? wireless flash memory with 3 volt i/o offers both hardware and software security features to protect the flash data. the software security feature is used by executing the lock block command. the hardware security feature is used by executing the lock-down block command and by asserting the wp# and v pp signals. for details on v pp data security, refer to section 5.4, ? write protection (v pp < v pplk ) ? on page 27 and section 6.2, ? erase protection (v pp < v pplk ) ? on page 28 . refer to figure 10, ? block locking state diagram for a state diagram of the flash security features. also see figure 35, ? locking operations flowchart ? on page 66 . notes: 1. the notation (x,y,z) denotes the locking state of a block, the current locking state of a block is defined by the state of wp# and the two bits of the block-lock status dq 1-0. 2. solid line indicates wp# asserted (low). dashed line indicates wp# unasserted (high). 8.1 block lock all blocks default to locked (states [001] or [101]) upon power-up or reset. locked blocks are fully protected from alteration. attempted program or erase operations to a locked block will return an error in status register bit sr.1. a locked block ? s status can be changed to unlocked or lock-down using the appropriate software commands. writing the lock block command sequence can lock an unlocked block. figure 10. block locking state diagram power-up or reset block locked block unlocked block locked- down (001) or (101) unlock cmd (000) initial lock-down cmd or assert wp # (011) lock cmd (001) unassert wp# (111) initial lock-down cmd or assert wp# (011) (x) (y) (z) wp# dq 1 dq 0 block status 0 0 0 unlocked 0 0 1 locked; default 0 1 0 invalid 0 1 1 locked down 1 0 0 unlocked 1 0 1 locked 1 1 0 unlocked 1 1 1 locked notes: 1.) x = wp# = write protect signal. 2.) y = dq 1 = lock-down status. 3.) z = dq 0 = lock status. unlock cmd (110) (101) (100) lock cmd (101)
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 30 preliminary 8.2 block unlock unlocked blocks (states [000], [100], [110]) can be programmed or erased. all unlocked blocks return to locked when the device is reset or powered down. an unlocked block can be locked or locked-down using the appropriate software commands. if it ? s not locked-down, a locked block can be unlocked by writing the unlock block command sequence. 8.3 lock-down block locked-down blocks (state [011]) are protected from program and erase operations, but unlike locked blocks, software commands alone cannot change their protection status. a locked-down block can only be unlocked when wp# is high. when wp# is low, all locked-down blocks revert to locked. a locked or unlocked block can be locked-down by writing the lock-down block command sequence. locked-down blocks revert to the locked state at device reset or power-down. 8.4 block lock operations during erase suspend block lock configurations can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. useful when another block requires immediate updating. to change block locking during an erase operation, first write the erase suspend command. after checking sr.6 to determine that the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. after completing lock, unlock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits will change immediately. but when resumed, the erase operation will complete. locking operations cannot occur during program suspend. appendix a, ? flash write state machine (wsm) ? shows valid commands during erase suspend. 8.5 wp# lock-down control wp# allows block lock-down to be overridden. table 14 defines device write protection methodology. wp# controls the lock-down function. wp# = v il (0) protects locked-down blocks [011] from program, erase, and lock status changes. when wp# = v ih (1), the locked-down blocks revert to locked [111]. a software command can then individually unlock a block [110] for erase or program. these blocks can then be re-locked [111] while wp# remains high. when wp# returns low, previously locked-down blocks revert to the lock-down state [011] regardless of changes made while wp# was high. device reset or power-down resets all blocks to the locked state [101] or [001].
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 31 . table 14. write protection truth table v pp wp# rst# write protection xxv il reset mode, device inaccessible v il xv ih program and erase prohibited > v pplk v il v ih all lock-down blocks are locked >v pplk v ih v ih all lock-down blocks are unlockable
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 32 preliminary 9.0 flash protection register the 1.8 volt intel ? wireless flash memory includes a 128-bit protection register. this protection register can be used to increase system security and/or for identification purposes. the protection register value can match the flash component to the system ? s cpu or asic to prevent device substitution. the lower 64-bit segments within the protection register are programmed by intel with a unique number in each flash device. the upper 64-bit segments within the protection register are left for the customer to program. once programmed, the customer segment can be locked to prevent further reprogramming. the protection register shares some of the same internal flash resources as the parameter partition. therefore, read-while-write is only allowed between the protection register and main partitions. table 15 describes the operation allowed using read-while-write/erase with the protection register. 9.1 protection register read writing the read identifier command allows the protection register data to be read 16 bits at a time from addresses shown in table 11, ? device identification codes ? on page 21 . the id plane, containing the protection registers, appears over partition addresses corresponding to the partition address supplied with the command. writing the read array command returns the device to read array mode. 9.2 program protection register the protection program command should be issued only at the bottom partition followed by the data to be programed at the specified location. it programs the 64-bit user protection register 16 bits at a time. table 11, ? device identification codes ? on page 21 and table 16, ? protection register table 15. simultaneous operations allowed with the protection register protection register parameter partition array data main partition notes read conditional ? see notes write/erase while programming or erasing in a main partition, the protection register may be read from any other partition. reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. conditional ? see notes read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers from parameter partition addresses is not allowed. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers in a partition that is different from the one being programed/erased, and also different from the parameter partition, is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to the parameter partition is not allowed. this is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. reads in other main partitions are supported.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 33 addressing? on page 33 show allowable addresses. see also figure 36, ?protection register programming flowchart? on page 67 . issuing a protection program command outside the register?s address space results in a status register error (sr.4 = 1). note: addresses a 17 ?a 8 should be set to zero. a max ?a 18 = partition base address (pba). 9.3 protection register lock the protection register ? s user-programmable segment is lockable by programming ? 0 ? to the pr-lock register bits ? 1 ? using the protection program command ( figure 11 ). pr-lock register bit ? 0 ? is programmed to 0 at the intel factory to protect the unique device number. pr-lock register bit ? 1 ? can be programmed by the user to lock the 64-bit user register. this bit is set using the protection program command to program ? fffdh ? into pr-lock register 0. after pr-lock register bits have been programmed, no further changes can be made to the protection register ? s stored values. protection program commands written to a locked section result in a status register error (program error bit sr.4 and lock error bit sr.1 are set to 1). once locked, protection register states are not reversible. table 16. protection register addressing word use id offset a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 word lock both pba+000080h 1 0 0 0 0 0 0 0 lock 0 intel pba+000081h 1 0 0 0 0 0 0 1 0 1 intel pba+000082h 1 0 0 0 0 0 1 0 1 2 intel pba+000083h 1 0 0 0 0 0 1 1 2 3 intel pba+000084h 1 0 0 0 0 1 0 0 3 4 customer pba+000085h 1 0 0 0 0 1 0 1 4 5 customer pba+000086h 1 0 0 0 0 1 1 0 5 6 customer pba+000087h 1 0 0 0 0 1 1 1 6 7 customer pba+000088h 1 0 0 0 1 0 0 0 7 figure 11. protection register locking lock register 0 4 words (64 bits) user programmed 1 word (16bits) 4 words (64 bits) intel factory programmed 0084h 0088h 0085h 0081h 0080h
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 34 preliminary 10.0 power and reset considerations 10.1 power-up/down characteristics in order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up v cc , v ccq and s-v cc together. conversely, v cc , v ccq and s-v cc must power-down together. it is also recommended to power-up v pp with or slightly after v cc . conversely, v pp must power- down with or slightly before v cc . if v ccq and/or v pp are not connected to the v cc supply, then v cc should attain v cc min before applying v ccq and v pp . device inputs should not be driven before supply voltage = v cc min. power supply transitions should only occur when rst# is low. 10.2 power supply decoupling when the device is accessed, many internal conditions change. circuits are enabled to charge pumps and voltages are switched. all this internal activity produces transient signals. the magnitude of these transient signals depends on the device and the system capacitive and inductive loading. to minimize the effect of these transient signals, a 0.1 f ceramic decoupling capacitor is required across each v cc , v ccq , v pp, s-v cc to system ground. capacitors should also be placed as close as possible to the package balls. 10.3 flash reset characteristics by holding the flash device in reset during power-up/down transitions, invalid bus conditions can be masked. the flash device enters a reset mode when rst# is driven low. in reset mode, internal flash circuitry is turned off and outputs are placed in a high-impedance state. after return from reset, a certain amount of time is required before the flash device is capable of performing normal operations. upon return from reset, the flash device defaults to page mode. if rst# is driven low during a program or erase operation, the operation will be aborted and the memory contents at the aborted block or address are no longer valid. see figure 24, ? reset operations waveforms ? on page 52 for detailed information regarding reset timings.
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 35 11.0 electrical specifications 11.1 absolute maximum ratings notes: 1. all specified voltages are with respect to v ss . minimum dc voltage is ?0.5 v on input/output signals and ?0.2 v on v cc and v pp supplies. during transitions, this level may undershoot to ?2.0 v for periods <20 ns which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods <20 ns. 3. v pp program voltage is normally v pp1 . v pp can be v pp2 for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. output shorted for no more than one second. no more than one output shorted at a time. warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 11.2 extended temperature operation parameter note maximum rating temperature under bias ? 25 c to +85 c storage temperature ? 65 c to +125 c voltage on any signals (except v cc , v ccq , v pp and s-v cc )1 ? 0.5 v to +3.80 v v pp voltage 1,2,3 ? 0.2 v to +14 v v cc voltage 1 ? 0.2 v to +2.40 v v ccq and s-v cc voltage 1 ? 0.2 v to +3.36 v output short circuit current 4 100 ma notice: this datasheet contains preliminary information on new products in production. specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . symbol parameter note min max unit t a operating temperature ? 25 85 c v cc v cc supply voltage 1.70 1.90 v v ccq , s-v cc flash i/o and sram supply voltages 2 2.20 3.30 v v pp1 v pp voltage supply (logic level) 1 0.90 1.90 v v pp2 factory programming v pp 1 11.4 12.6 t pph maximum v pp hours v pp = v pp2 1 80 hours block erase cycles main and parameter blocks v pp = v cc 1 100,000 cycles main blocks v pp = v pp2 1 1000 parameter blocks v pp = v pp2 1 2500
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 36 preliminary notes: 1. in normal operation, the v pp program voltage is v pp1 . v pp can be connected to 11.4 v ? 12.6 v for 1000 cycles on main blocks for extended temperatures and 2500 cycles at extended temperature on parameter blocks. 2. v ccq and s-v cc must be tied together, except when in data retention mode. 11.3 dc characteristics sym parameter (1) devic e note min typ max unit test condition i li input load current flash/ sram 12a v cc = v cc max v ccq = v ccq max s-v cc = s-v cc max inputs = v ccq or v ss i lo output leakage current dq 15-0 , wait flash/ sram 110a i ccs standby current flash 1 6 21 a v cc = v cc max v ccq = v ccq max ce# = v cc rst# =v cc or v ss 4-mbit sram 120a s-v cc = s-v cc max s-cs 1 # = s-v cc s-cs 2 = s-v cc or s-v ss inputs = s-v cc or s-v ss 8-mbit sram 140a i cc operating power supply current (cycle time = 1 s) 4-mbit sram 110mai io = 0 ma, s-cs 1 # = v il s-sc 2 = s-we# = v ih inputs = v il or v ih 8-mbit sram 120ma i cc2 operating power supply current (min cycle time) 4-mbit sram 145ma cycle time = min 100% duty i io = 0 ma, s-cs 1 # = v il s-sc 2 = v ih inputs = v il or v ih 8-mbit sram 165ma i ccr average v cc read current asynchronous page mode read flash 2 4 7 ma 4-word read v cc = v cc max ce# = v il oe# = v ih inputs = v ih or v il synchronous clk = 40 mhz flash 2, 3 715ma 4 -word burst 9 16 ma 8-word burst 12 22 ma continuous burst i ccw v cc program current flash 4, 5 18 40 ma v pp = v pp1 815mav pp = v pp2 i cce v cc block erase current flash 4, 6 18 40 ma v pp = v pp1 815mav pp = v pp2 i ccws v cc program suspend current flash 4 6 21 a ce# = v ccq i cces v cc erase suspend current flash 4, 7 6 21 a ce# = v cc
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 37 notes: 1. all currents are rms unless noted. typical values at typical v cc , t a = +25 c. 2. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation. 3. the burst wrap bit (cr.3) determines whether 4-, or 8-word burst accesses wrap within the burst-length boundary, or whether they cross word-length boundaries to perform linear accesses. in the no-wrap mode (cr.3 = 1), the device operates similar to continuous linear burst mode, but consumes less power. 4. sampled, not 100% tested. 5. v cc read + program current is the summation of v cc read and v cc program currents. 6. v cc read + erase current is the summation of v cc read and v cc block erase currents. 7. i cces is specified with device deselected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . 8. erase and program operations are inhibited when v pp v pplk and not guaranteed outside valid v pp1 and v pp2 ranges. 9. v il can undershoot to ? 0.4 v and v ih can overshoot to v ccq + 0.4 v for durations of 20 ns or less. ac i/o test conditions i pps (i ppws, i ppes ) v pp standby current v pp program suspend current v pp erase suspend current flash 4 0.2 5 a v pp1 v cc i ppr v pp read current flash 2 15 a v pp v cc i ppw v pp program current flash 4 0.05 0.10 ma v pp = v pp1 822 v pp = v pp2 i ppe v pp erase current flash 4 0.05 0.10 ma v pp = v pp1 822 v pp = v pp2 v il input low voltage flash / sram 90 0.4v v ih input high voltage flash / sram 9 v ccq - 0.4 v ccq v v ol output low voltage flash / sram 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage flash / sram v ccq - 0.1 v v cc = v cc min v ccq = v ccq min i oh = ? 100 a v pplk v pp lock-out voltage flash 8 0.4 v v lko v cc lock voltage flash 1.0 v v lkoq v ccq lock-out voltage flash 0.90 v sym parameter (1) devic e note min typ max unit test condition
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 38 preliminary notes: 1. ac test inputs are driven at v ccq for a logic ?1? and 0.0 v for a logic ?0.? input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v cc = v cc min. 2. timing conditions apply to both flash and sram. notes: 1. see table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance. 11.4 discrete capacitance (32-mbit vf bga package) t a = +25c, f = 1 mhz note: 1. sampled, not 100% tested. figure 12. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output figure 13. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 out test configuration c l (pf) r 1 ( ? )r 2 ( ? ) v ccq min standard test 30 25k 25k sym parameter (1) typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v c ce ce# input capacitance 10 12 pf v in = 0.0 v
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 39 11.5 stacked capacitance (32/4 and 64/8 stacked-csp package) t a = +25 c, f = 1 mhz note: 1. sampled, not 100% tested. sym parameter (1) typ max unit condition c in input capacitance 16 18 pf v in = 0.0 v c out output capacitance 18 22 pf v out = 0.0 v c ce ce# input capacitance 10 12 pf v in = 0.0 v
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 40 preliminary 12.0 flash ac characteristics 12.1 flash read operations # sym parameter (1,2) speed ? 70 ? 85 unit note min max min max r1 t avav read cycle time 3 70 85 ns r2 t avqv address to output delay 3 70 85 ns r3 t elqv ce# low to output delay 70 85 ns r4 t glqv oe# low to output delay 5 30 30 ns r5 t phqv rst# high to output delay 150 150 ns r7 t glqx oe# low to output in low-z 5, 6 0 0 ns r8 t ehqz ce# high to output in high-z 6 25 25 ns r9 t ghqz oe# high to output in high-z 5, 6 25 25 ns r10 t oh ce#, (oe#) high to output in low-z 5, 6 0 0 ns r101 t avvh address setup to adv# high 10 10 ns r102 t elvh ce# low to adv# high 10 10 ns r103 t vlqv adv# low to output delay 70 85 ns r104 t vlvh adv# pulse width low 10 10 ns r105 t vhvl adv# pulse width high 6 10 10 ns r106 t vhax address hold from adv# high 4 9 9 ns r108 t apa page address access time 4 25 25 ns r200 f clk clk frequency 40 33 mhz r201 t clk clk period 25 30 ns r202 t ch/l clk high or low time 9.5 9.5 ns r203 t chcl clk fall or rise time 3 5 ns r301 t avch address valid setup to clk 9 9 ns r302 t vlch adv# low setup to clk 10 10 ns r303 t elch ce# low setup to clk 9 9 ns r304 t chqv clk to output delay 20 22 ns r305 t chqx output hold from clk 5 5 ns r306 t chax address hold from clk 4 10 10 ns r307 t chtl/ h clk to wait asserted 20 22 ns r308 t eltl oe# low to wait active 7 20 22 ns r309 t ehtz ce# (oe#) high to wait high-z 6, 7 25 25 ns r310 t ehel ce# pulse width high 7 20 20 ns
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 41 notes: 1. see figure 12, ? ac input/output reference waveform ? on page 38 for timing measurements and maximum allowable input slew rate. 2. ac specifications assume the data bus voltage is less than or equal to v ccq when a read operation is initiated. 3. t avav = 85 ns for 128-mbit device. 4. address hold in synchronous burst-mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 5. oe# may be delayed by up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . 6. sampled, not 100% tested. 7. applies only to subsequent synchronous reads. figure 14. single word asynchronous read waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r7 r10 generic_async_rd address [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] r8 r9
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 42 preliminary figure 15. single word latched asynchronous read waveform v oh v ol high z valid output v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il data [d/q] we# [w] oe# [g] ce# [e] amax-2 [a] adv# [v] rst# [p] r102 r104 r1 r2 r3 r4 r5 r7 r10 r103 r101 r105 r106 generic_latch_async_rd a 1-0 [a] v ih v il valid address valid address valid address r8 r9
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 43 figure 16. page mode read waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] a max-2 [a] a 1-0 [a] r1 r2 r101 r106 r103 r3 r4 r7 r108 r10 generic_pg_rd r5 r9 r8
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 44 preliminary notes: 1. section 4.2.2, ? first latency count (lc2 ? 0) ? on page 14 describes how to insert clock cycles during the initial access. 2. wait (shown active low) can be configured to assert either during or one data cycle before valid data. figure 17. single word burst read waveform generic_1w_sync_rd note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [d/q] ce# [e] r303 r104 high z r308 r309 note 2
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 45 notes: 1. section 4.2.2, ? first latency count (lc2 ? 0) ? on page 14 describes how to insert clock cycles during the initial access. 2. wait (shown active low) can be configured to assert either during or one data cycle before valid data. figure 18. 4 word burst read waveform v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il valid address v ih v il note 1 v oh v ol valid output valid output valid output valid output high z r105 r102 r301 r302 r306 r101 r2 r106 r103 r3 r4 r7 r304 r5 r305 r8 r9 01 rst# [p] wait [t] we# [w] oe# [g] ce# [e] adv# [v] address [a] clk [c] data [d/q] note 2 r104 r303 r10 r307 high z r308 r309 r310 high z high z figure 19. clock input ac waveform clk [c] v ih v il r203 r202 r201 clkinput.wmf
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 46 preliminary notes: 1. wait signal is in ? asserted ? state. 2. wait shown active low. figure 20. wait signal in synchronous non-read-array operation waveform note 1 v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il v oh v ol v oh v ol high z valid output v ih v il r101 r102 r302 r301 r306 r2 r106 r105 r103 r3 r4 r7 r8 r9 r10 r5 r305 high z r304 clk [c] rst# [p] address [a] adv# [v] oe# [g] we# [w] wait [t] data [d/q] ce# [e] r303 r104 high z r308 r309 note 2
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 47 notes: 1. wait signal is in ? asserted ? state. 2. wait shown active low. figure 21. wait signal in asynchronous page-mode read operation waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] a max-2 [a] a 1-0 [a] r1 r2 r101 r106 r103 r3 r107 r4 r7 r6 r108 r10 r5 r9 r8 v oh v ol high z wait [t] high z note 2
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 48 preliminary notes: 1. wait signal is in ? asserted ? state. 2. wait shown active low. figure 22. wait signal in asynchronous single-word read operation waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r6 r7 r10 address [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] r8 r9 v oh v ol high z wait [t] high z note 2
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 49 12.2 flash write operations notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first); hence, t wp = t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever is first) to ce# or we# low (whichever is last). hence, t wph = t whwl = t ehel = t whel = t ehwl . 6. system designers should take this into account and may insert a software no-op instruction to delay the first read after issuing a command. 7. for commands other than resume commands. 8. v pp should be held at v pp1 or v pp2 until block erase or program success is determined. # sym parameter (1,2) speed ? 70 ? 85 unit note min max min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) low 150 150 ns w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) low 0 0 ns w3 t wlwh (t eleh ) we# (ce#) write pulse width low 4 45 60 ns w4 t dvwh (t dveh ) data setup to we# (ce#) high 45 60 ns w5 t avwh (t aveh ) address setup to we# (ce#) high 45 60 ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 0 ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 0 0 ns w8 t whax (t ehax ) address hold from we# (ce#) high 0 0 ns w9 t whwl (t ehel ) we# (ce#) pulse width high 5, 6, 7 25 25 ns w10 t vpwh (t vpeh ) v pp setup to we# (ce#) high 3 200 200 ns w11 t qvvl v pp hold from valid status register data 3, 8 0 0 ns w12 t qvbl wp# hold from valid status register data 3, 8 0 0 ns w13 t bhwh (t bheh ) wp# setup to we# (ce#) high 3 200 200 ns w14 t whgl (t ehgl ) write recovery before read 0 0 ns w16 t whqv we# high to valid data 6 t avqv + 40 t avqv + 50 ns
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 50 preliminary note: 1. v cc power-up and standby. 2. write program or erase setup command. 3. write valid address and data (for program) or erase confirm command. 4. automated program/erase delay. 5. read status register data (srd) to determine program/erase operation completion. 6. oe# and ce# must be driven active (low) and we# must be de-asserted (high) for read operations. figure 23. write waveform note 1 note 2 note 3 note 4 note 5 address [a] v ih v il valid address valid address ce# (we#) [e(w)] v ih v il note 6 oe# [g] v ih v il we# (ce#) [w(e)] v ih v il rst# [p] v ih v il w6 w7 w8 w11 w12 v pp [v] v pp1/2 v pplk v il wp# [b] v ih v il data [d/q] v ih v il data in valid data adv# [v] v ih v il w16 w1 w2 w3 w5 w9 w10 w13 w14 data in valid address note 6 w4
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 51 12.3 flash program and erase operations notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes external system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. 5. exact results may vary based on system overhead. 12.4 reset operations notes: 1. these specifications are valid for all product versions (packages and speeds). 2. the device may reset if t plph is =v cc min. extended temperatures f-v pp1 f-v pp2 unit # operation symbol parameter notes typ max typ max w0 program time t whqv1 / t ehqv1 word 1-word 1,2,3,4 12 150 8 130 s enhanced factory programming mode 1,3,4 n/a n/a 3.5 16 t bwpb block 4-kw parameter 1,2,3,4 0.05 0.23 0.03 0.07 s t bwmb 32-kw main 1,2,3,4 0.4 1.8 0.24 0.6 s t bwpb efp mode 4-kw parameter 1,2,3,4, 5 n/a n/a 0.015 n/a s t bwmb 32-kw main 1,2,3,4, 5 n/a n/a 0.12 n/a s erase time t whqv2 / t ehqv2 block 4-kw parameter 1,2,3,4 0.3 2.5 0.25 2.5 s 32-kw main 1,2,3,4 0.7 4 0.4 4 s suspend latency t whrh1 / t ehrh1 program suspend 1,2,3,4 5 10 5 10 s t whrh2 / t ehrh2 erase suspend 1,2,3,4 9 20 9 20 efp latency t efp-setup efp setup 1,3,4 n/a n/a n/a 5 s t efp-tran program to verify transition 1,3,4 n/a n/a 2.7 5.6 t efp-verify verify 1,3,4 n/a n/a 1.7 130 # symbol parameter note min max unit p1 t plph rst# low to reset during read 1, 2, 3, 4 100 ns p2 t plrh rst# low to reset during block erase 1, 3, 4, 5 20 s rst# low to reset during program 1, 3, 4, 5 10 p3 t vccph v cc power valid to rst# high 1, 3, 4, 5, 6 60
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 52 preliminary 6. if rst# tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until after v cc >=v cc min. figure 24. reset operations waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5 reset.wmf
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 53 13.0 sram ac characteristics 13.1 sram read operation note: 1. see figure 25, ? ac waveform: sram read operation ? on page 54 . 2. sampled, but not 100% tested. 3. at any given temperature and voltage condition, t hz (max) is less than t lz (max) for a given device and from device-to-device interconnection. 4. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. # sym parameter 1 density 4/8 mbit unit s-v cc 2.2 v ? 3.3 v speed -70 -85 note min max min max r1 t rc read cycle time 70 ? 85 ? ns r2 t aa address to output delay ? 70 ? 85 ns r3 t co1, t co2 s-cs 1 #, s-cs 2 to output delay ? 70 ? 85 ns r4 t oe s-oe# to output delay ? 35 ? 40 ns r5 t ba s-ub#, s-lb# to output delay ? 70 ? 85 ns r6 t lz1 , t lz2 s-cs 1 #, s-cs 2 to output in low-z 2, 3 5 ? 5 ? ns r7 t olz s-oe# to output in low-z 2 0 ? 0 ? ns r8 t hz1 , t hz2 s-cs 1 #, s-cs 2 to output in high-z 2, 3, 4 0 25 0 30 ns r9 t ohz s-oe# to output in high-z 2, 4 0 25 0 30 ns r10 t oh output hold from address, s-cs 1 #, s-cs 2 , or s-oe# change, whichever occurs first 0 ? 0 ? ns r11 t blz s-ub#, s-lb# to output in low-z 2 0 ? 0 ? ns r12 t bhz s-ub#, s-lb# to output in high-z 2 0 25 0 30 ns
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 54 preliminary figure 25. ac waveform: sram read operation high z valid output address stable data valid device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il r1 r2 r4 r3 r6 r7 r8 r9 r10 cs 2 (e 2 ) v ih v il v ih r5 r11 r12
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 55 13.2 sram write operation notes: 1. see figure 26, ? ac waveform: sram write operation ? on page 56 . 2. a write occurs during the overlap (t wp ) of low s-cs 1 # and low s-we#. a write begins when s-cs 1 # goes low and s-we# goes low with asserting s-ub# and s-lb# for x16 operation. s-ub# and s-lb# must be tied together to restrict x16 mode. a write ends at the earliest transition when s-cs 1 # goes high and s-we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t cw is measured from s-cs 1 # going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change; t wr applied in case a write ends as s-cs 1 # or s-we# going high. # sym parameter 1 density 4/8 mbit unit s-v cc 2.2 v ? 3.3 v speed -70 -85 note min max min max w1 t wc write cycle time 2 70 ? 85 ? ns w2 t as address setup to s-we# (s-cs 1 #) and s-ub#, s-lb# going low 4 0 ? 0 ? ns w3 t wp s-we# (s-cs 1 #) pulse width 3 55 ? 60 ? ns w4 t dw data to write time overlap 30 ? 35 ? ns w5 t aw address setup to s-we# (s-cs 1 #) going high 60 ? 70 ? ns w6 t cw s-sc 1 # (s-we#) setup to s-we# (s-cs 1 #) going high and s-sc 2 going low 60 ? 70 ? ns w7 t dh data hold time from s-we# (s-cs 1 #) high 0 ? 0 ? ns w8 t wr write recovery 5 0 ? 0 ? ns w9 t bw s-ub#, s-lb# setup to s-we# (s-cs 1 #) going high 60 ? 70 ? ns
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 56 preliminary 13.3 sram data retention operation notes: 1. typical values at nominal s-v cc , t a = +25 c. 2. s-cs 1 # > s-v cc ? 0.2 v, s-cs 2 > s-v cc ? 0.2 v (s-cs 1 # controlled) or s-cs 2 < 0.2 v (s-cs 2 controlled). figure 26. ac waveform: sram write operation sym parameter device note min typ max unit test conditions v dr s-v cc for data retention 4/8- mbit 1, 2 1.5 ? 3.3 v s-cs 1 # s-v cc ? 0.2 v i dr data retention current 4-mbit 1, 2 ?? 5 a s-vcc = 1.5 v s-cs 1 # s-v cc ? 0.2 v 8-mbit ?? 25 t sdr data retention setup time 4/8- mbit 10 ?? ns see data retention waveform t rdr recovery time 4/8- mbit 1t rc ?? ns high z data in address stable device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il w1 w8 cs 2 (e 2 ) v ih v il v ih w9 w6 w5 w2 w3 w4 w7
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 57 figure 27. sram data retention waveform s-v ss v dr s-cs 1 # (e1) s-v cc v ihmax v ihmin data retention mode t sdr t rdr s-v ss v ilmax s-cs 2 (e 2 ) s-v cc v ihmin v dr data retention mode t sdr t rdr s-cs2 controlled s-cs 1 # s-cs 1 # controlled s-cs 2
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 58 preliminary 14.0 ordering information figure 28. component ordering breakdown table 17. valid component combinations stacked-csp vf bga bga* 32m rd28f3204w30t70 rd28f3204w30b70 rd28f3204w30t85 rd28f3204w30b85 ge28f320w30t70 GE28F320W30B70 ge28f320w30t85 ge28f320w30b85 64 m rd28f6408w30t70 rd28f6408w30b70 rd28f6408w30t85 rd28f6408w30b85 gt28f640w30t70 gt28f640w30b70 gt28f640w30t85 gt28f640w30b85 128 m tbd tbd r d 2 8 f 6 4 0 8 w t 7 0 package designator, extended temperature (-25 c to +85 c) ge = 0.75 mm vf bga rd = stacked csp gt = 0.75 mm bga* product line designator for all intel ? flash products access speed 70 ns 85 ns product family w30 = 1.8 volt intel ? wireless flash memory with 3 volt i/o and sram v cc = 1.70 v - 1.90 v v ccq = 2.20 v - 3.30 v flash density 320 = x16 (32-mbit) 640 = x16 (64-mbit) 128 = x16 (128-mbit) parameter partition t = top parameter device b = bottom parameter device sram density for stacked-csp products only 4 = x16 (4-mbit) 8 = x16 (8-mbit) 3 0
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 59 appendix a flash write state machine (wsm) this table shows the command state transitions based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition ? s output state. figure 29. write state machine ? next state table (sheet 1 of 2) chip next state after command input read array (3) program setup (4,5) erase setup (4,5) enhanced factory pgm setup (4) be confirm, p/e resume, ulb confirm (9) program/ erase suspend read status clear status register (6) read id/query (ffh) (10h/40h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h) ready ready program setup erase setup efp setup ready lock/cr setup ready (lock error) ready ready (lock error) setup otp busy busy setup program busy busy program busy pgm susp program busy suspend program suspend pgm busy program suspend setup ready (error) erase busy ready (error) busy erase busy erase susp erase busy suspend erase suspend pgm in erase susp setup erase suspend erase busy erase suspend setup program in erase suspend busy busy program in erase suspend busy pgm susp in erase susp program in erase suspend busy suspend program suspend in erase suspend pgm in erase susp busy program suspend in erase suspend erase suspend (lock error) erase susp erase suspend (lock error) setup ready (error) efp busy ready (error) efp busy efp busy (7) efp verify verify busy (7) output next state after command input status status status id/query write state machine (wsm) next state table output next state table (1) lock/cr setup, lock/cr setup in erase susp otp busy current chip state (8) ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm susp in erase susp pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify busy lock/cr setup in erase suspend erase program program in erase suspend otp enhanced factory program output does not change array (3) status output does not change status
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 60 preliminary notes: 1. the output state shows the type of data that appears at the outputs if the partition address is the same as the command address. a partition can be placed in read array, read status or read id/cfi, depending on the command issued. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition ? s output state. for example, if partition #1 ? s output state is read array and partition #4 ? s output state is read status, every read from partition #4 (without issuing a new command) outputs the status register. 2. illegal commands are those not defined in the command set. 3. all partitions default to read array mode at power-up. a read array command issued to a busy partition results in undermined data when a partition address is read. 4. both cycles of 2-cycle commands should be issued to the same partition address. if they are issued to different partitions, t he second write determines the active partition. both partitions will output status information when read. 5. if the wsm is active, both cycles of a 2-cycle command are ignored. this differs from previous intel devices. 6. the clear status command clears status register error bits except when the wsm is running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, efp modes) or suspended (erase suspend, pgm suspend, pgm suspend in erase suspend). 7. efp writes are allowed only when status register bit sr.0 = 0. efp is busy if block address = address at efp confirm command. any other commands are treated as data. 8. the ? current state ? is that of the wsm, not the partition. 9. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. figure 29. write state machine ? next state table (sheet 2 of 2) chip next state after command input lock, unlock, lock-down, cr setup (5) otp setup (5) lock block confirm (9) lock- down block confirm (9) write cr confirm (9) enhanced fact pgm exit (blk add <> wa0) illegal commands or efp data (2) (60h) (c0h) (01h) (2fh) (03h) (xxxxh) (other codes) ready lock/cr setup otp setup ready lock/cr setup ready (lock error) ready ready ready ready (lock error) setup o tp b usy busy ready setup program busy n/a busy program busy ready suspend program suspend setup ready (error) busy erase busy erase busy ready suspend lock/cr setup in erase susp erase suspend setup program in erase suspend busy busy program in erase suspend busy erase suspend suspend program suspend in erase suspend erase suspend (lock error) erase susp erase susp erase susp erase suspend (lock error) setup ready (error) efp busy efp busy (7) efp verify efp busy (7) efp verify verify busy (7) ready efp verify (7) ready output next state after command input status status array status write state machine (wsm) next state table output next state table (1) program erase program in erase suspend current chip state (8) otp lock/cr setup in erase suspend enhanced factory program output does not change output does not change wsm operation completes n/a n/a n/a n/a output does not change array status pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify b usy lock/cr setup, lock/cr setup in erase susp otp busy ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm s usp in e rase susp
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 61 appendix b flowcharts figure 30. programming flowchart suspend program loop start write 40h, word address write data word address read status register sr.7 = full status check (if desired) program complete full status check procedure suspend program read status register program successful sr.3 = sr.1 = 0 0 sr.4 = 0 1 1 1 1 0 no yes v pp range error device protect error program error word program procedure sr.3 must be cleared before the write state machine will allow further program attempts only the clear staus register command clears sr.1, 3, 4. if an error is detected, clear the status register before attempting a program retry or other error recovery. standby standby bus operation command check sr.3 1 = v pp error check sr.4 1 = data program error comments repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. write ffh after the last operation to enter read array mode. comments bus operation command data = 40h addr = location to program (wa) write program setup data = data to program (wd) addr = location to program (wa) write data status register data. toggle ce# or oe# to update status register read check sr.7 1 = wsm ready 0 = wsm busy standby standby check sr.1 1 = attempted program to locked block program aborted pgm_wrd.wmf program word data/ confirm
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 62 preliminary figure 31. program suspend/resume flowchart read status register sr.7 = sr.2 = write ffh susp partition read array data program completed done reading write ffh pgm ? d partition write d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure write program resume data = d0h addr = suspended block (ba) bus operation command comments write program suspend data = b0h addr = block to suspend (ba) standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed write read array data = ffh addr = block address to read (ba) read read array data from block other than the one being programmed read status register data toggle ce# or oe# to update status register addr = suspended block (ba) pgm_sus.wmf start write b0h any address program suspend read status program resume read array read array write 70h same partition write read status data = 70h addr = same partition if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 70h addr = same partition write 70h same partition read status
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 63 figure 32. enhanced factory program flowchart efp setup efp program efp verify efp exit 1. wa 0 = first word address to be programmed within the target block. the bba (block base address) must remain constant throughout the program phase data stream; wa can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. writing to a bba not equal to that of the block currently being written to terminates the efp program phase, and instructs the device to enter the efp verify phase. 2. for proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. writing to a bba not equal to wa terminates the efp verify phase, and instructs the device to exit efp . 3. bits that did not fully program with the single wsm pulse of the efp program phase receive additional program-pulse attempts during the efp verify phase. the device will report any program failure by setting sr.4=1; this check can be performed during the full status check after efp has been exited for that block, and will indicate any error within the entire data stream. comments bus state repeat for subsequent operations. after efp exit, a full status check can determine if any program error occurred. see the full status check procedure in the word program flowchart. write standby read write write (note 2) read standby write read standby efp setup program done? exit program phase last data? exit verify phase efp exited? write efp confirm read standby efp setup done? read standby verify stream ready? write unlock block write (note 1) standby last data? standby (note 3) verify done? sr.0=1=n write data address = wa 0 last data? write ffffh address bba program done? read status register sr.0 = 0 = y y sr.0=1=n n write data address = wa 0 verify done? last data? read status register write ffffh address bba y verify stream ready? read status register sr.7=0=n full status check procedure operation complete read status register efp exited? sr.7 = 1 = y sr.0=1=n start write 30h address = wa 0 v pp = 12v unlock block write d0h address = wa 0 efp setup done? read status register sr.7 = 1 = n exit n efp program efp verify efp exit efp setup enhanced factory programming procedure comments bus state data = 30h address = wa 0 data = d0h address = wa 0 status register check sr.7 0 = efp ready 1 = efp not ready v pp = 12v unlock block check sr.0 0 = program done 1 = program not done status register data = ffffh address not within same bba data = data to program address = wa 0 device automatically increments address. comments bus state data = word to verify address = wa 0 status register device automatically increments address. data = ffffh address not within same bba status register check sr.0 0 = ready for verify 1 = not ready for verify check sr.0 0 = verify done 1 = verify not done status register check sr.7 0 = exit not finished 1 = exit completed check v pp & lock errors (sr.3, sr.1) data stream ready? read status register sr.0 = 0 = y sr.7=0=y sr.0=1=n standby read data stream ready? check sr.0 0 = ready for data 1 = not ready for data status register sr.0 = 0 = y sr.0 = 0 = y efp setup time standby setup time refer to program and erase operations table. standby error condition check if sr.7 = 1: check sr.3, sr.1 sr.3 = 1 = v pp error sr.1 = 1 = locked block
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 64 preliminary figure 33. block erase flowchart start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to enter read array mode. sr. 1 and 3 must be cleared before the write state machine will allow further erase attempts. only the clear staus register command clears sr.1, 3, 4, 5. if an error is detected, clear the status register before attempting an erase retry or other error recovery. no suspend erase 1 0 0 0 1 1 1 1 0 yes suspend erase loop 0 write 20h block address write d0h and block address read status register sr.7 = full erase status check (if desired) block erase complete read status register block erase successful sr.1 = erase of locked block aborted block erase procedure bus operation command comments write block erase setup data = 20h addr = block to be erased (ba) write erase confirm data = d0h addr = block to be erased (ba) read status register data. toggle ce# or oe# to update status register data standby check sr.7 1 = wsm ready 0 = wsm busy bus operation command comments sr.3 = v pp range error sr.4,5 = command sequence error sr.5 = block erase error standby check sr.3 1 = v pp error standby check sr.4,5 both 1 = command sequence error standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block erase aborted eras_blk.wmf block erase erase confirm
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 65 figure 34. erase suspend/resume flowchart erase completed write ffh erased partition read array data 0 0 no read 1 program program loop read array data 1 yes start write b0h any address read status register sr.7 = sr.6 = write d0h any address erase resumed read or program? done? write write standby standby write erase suspend read array or program program resume data = b0h addr = any address data = ffh or 40h addr = block to program or read check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = any address bus operation command comments read status register data. toggle ce# or oe# to update status register addr = same partition read or write read array or program data from/to block other than the one being erased erase suspend / resume procedure eras_sus.wmf write 70h same partition write read status data = 70h addr = same partition erase resume erase suspend read status read array write 70h same partition read status if the suspended partition was placed in read array mode or a program loop: write read status return partition to status mode: data = 70h addr = same partition
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 66 preliminary figure 35. locking operations flowchart no optional start write 60h block address write 90h read block lock status locking change? lock change complete write 01,d0,2fh block address write ffh partition address yes write write write (optional) read (optional) standby (optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = block address offset +2 (ba+2) block lock status data addr = block address offset +2 (ba+2) confirm locking change on dq 1 , dq 0 . (see block locking state transitions table for valid combinations.) data = ffh addr = block address (ba) bus operation command comments locking operations procedure lock_op.wmf lock confirm lock setup read id plane read array
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 67 figure 36. protection register programming flowchart full status check procedure protection program operations addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. write ffh after the last operation to enter read array mode. sr.3 must be cleared before the write state machine will allow further program attempts. only the clear staus register command clears sr.1, 3, 4. if an error is detected, clear the status register before attempting a program retry or other error recovery. yes no 1,1 0,1 1,1 protection register programming procedure start write c0h addr=prot addr write protect. register address / data read status register sr.7 = 1? full status check (if desired) program complete read status register data program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = v pp range error programming error locked-register program aborted standby standby bus operation command sr.1 sr.3 sr.4 011v pp error 0 0 1 prot. reg. prog. error comments write write standby protection program setup protection program data = c0h addr = first location to program data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy bus operation command comments read status register data toggle ce# or oe# to update status register data standby 1 0 1 register locked: aborted protflow.wmf program setup confirm data
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 68 preliminary appendix c common flash interface this appendix defines the data structure or ? database ? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. c.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device ? s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq0-7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ? q ? and ? r, ? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ? q ? in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ? h ? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ? 00h, ? the leading ? 00 ? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table c1. summary of query structure output as a function of device and mode table c2. example of query structure output of x16- and x8 devices device hex offset hex code ascii value 00010: 51 "q" device addresses 00011: 52 "r" 00012: 59 "y" word addressing: byte addressing: offset hex code value offset hex code value a ? a d ? d a ? a d ? d 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id prvendor 00013h p_id prvendor 00014h p_id id # 00014h p_id id # 00015h p prvendor 00015h p_id id # 00016h p tbladr 00016h ... ... 00017h a_id lo altvendor 00017h 00018h a_id hi id # 00018h ... ... ... ...
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 69 c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ? database. ? the structure subsections and address locations are summarized below. table c3. query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1 ? s beginning location when the block size is 32k-word). 3. offset 15 defines ? p ? which points to the primary intel-specific extended query table. c.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the v cc supply was not accidentally removed during an erase operation. only issuing another operation to the block resets this bit. the block status register is accessed from word address 02h within each block. table c4. block status register note: ba = the beginning location of a block address (i.e., 008000h is block 1 ? s (64kb block) beginning location in word mode). offset sub-section name (1) 00000h manufacturer code 00001h device code (2) block status register block-specific information 00004-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm offset length description add. value (ba+2)h (1) 1 block lock status register ba+2 --00 or --01 bsr.0 block lock status 0 = unlocked 1 = locked ba+2 (bit 0): 0 or 1 bsr.1 block lock-down status 0 = not locked down 1 = locked down ba+2 (bit 1): 0 or 1 bsr 2 ? 7: reserved for future use ba+2 (bit 2 ? 7): 0
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 70 preliminary c.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table c5. cfi identification table c6. system interface information offset length description add. hex code value 10h 3 query-unique ascii string ? qry ? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --03 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --39 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --19 1.9v 1dh 1 1d: --b4 11.4v 1eh 1 1e: --c6 12.6v 1fh 1 ? n ? such that typical single word program time-out = 2 n -sec 1f: --04 16s 20h 1 ? n ? such that typical max. buffer write time-out = 2 n -sec 20: --00 na 21h 1 ? n ? such that typical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ? n ? such that typical full chip erase time-out = 2 n m-sec 22: --00 na 23h 1 ? n ? such that maximum word program time-out = 2 n times typical 23: --04 256s 24h 1 ? n ? such that maximum buffer write time-out = 2 n times typical 24: --00 na 25h 1 ? n ? such that maximum block erase time-out = 2 n times typical 25: --03 8s 26h 1 ? n ? such that maximum chip erase time-out = 2 n times typical 26: --00 na v pp [programming] supply minimum program/erase voltage bits 0 ? 3 bcd 100 mv bits 4 ? 7 hex volts v pp [programming] supply maximum program/erase voltage bits 0 ? 3 bcd 100 mv bits 4 ? 7 hex volts v cc logic supply minimum program/erase voltage bits 0 ? 3 bcd 100 mv bits 4 ? 7 bcd volts v cc logic supply maximum program/erase voltage bits 0 ? 3 bcd 100 mv bits 4 ? 7 bcd volts
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 71 c.5 device geometry definition table c7. device geometry definition offset length description code 27h 1 ? n ? such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 x1k x512 x256 x128 x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ???????? 29: --00 2ah 2 ? n ? such that maximum number of bytes in write buffer = 2 n 2a: --00 0 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information - bottom paramenter device 2d: erase block region x-3 information - top paramenter device 2e: bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 2f: bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 30: 31h 4 erase block region 2 information 31: bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 32: bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 erase block region 3-x information for bottom parameter device 35: erase block region 1 information for top paramenter device 36: bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 37: bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 38: see table below number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ? bulk ? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: see table below see table below see table below address 16 mbit 32 mbit ? b ? t ? b ? t ? b ? t ? b ? t 27: --15 --15 --16 --16 --17 --17 --18 --18 28: --01 --01 --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 --00 --00 2a: --00 --00 --00 --00 --00 --00 --00 --00 2b: --00 --00 --00 --00 --00 --00 --00 --00 2c: --05 --05 --09 --09 --11 --11 --21 --21 2d: --07 --07 --07 --07 --07 --07 --07 --07 2e: --00 --00 --00 --00 --00 --00 --00 --00 2f: --20 --00 --20 --00 --20 --00 --20 --00 30: --00 --01 --00 --01 --00 --01 --00 --01 31: --06 --06 --06 --06 --06 --06 --06 --06 32: --00 --00 --00 --00 --00 --00 --00 --00 33: --00 --00 --00 --00 --00 --00 --00 --00 34: --01 --01 --01 --01 --01 --01 --01 --01 35: --07 --07 --07 --07 --07 --07 --07 --07 36: --00 --00 --00 --00 --00 --00 --00 --00 37: --00 --20 --00 --20 --00 --20 --00 --20 38: --01 --00 --01 --00 --01 --00 --01 --00 64 mbit 128 mbit
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 72 preliminary c.6 intel-specific extended query table table c8. primary vendor-specific extended query (1) length description hex p = 39h (optional flash features and commands) add. code value (p+0)h 3 primary extended query table 39: --50 "p" (p+1)h unique ascii string ? pri ? 3a: --52 "r" (p+2)h 3b: --49 "i" (p+3)h 1 major version number, ascii 3c: --31 "1" (p+4)h 1 minor version number, ascii 3d: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 3e: --e6 (p+6)h bits 10 ? 31 are reserved; undefined bits are ? 0. ? if bit 31 is 3f: --03 (p+7)h ? 1 ? then another 31 bit field of optional features follows at 40: --00 (p+8)h the end of the bit ? 30 field. 41: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1 ? 7 reserved; undefined bits are ? 0 ? 42: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 43: --03 (p+b)h bits 2 ? 15 are reserved; undefined bits are ? 0 ? 44: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0 ? 3 bcd value in 100 mv 45: --18 1.8v (p+d)h 1 v pp optimum program/erase supply voltage bits 0 ? 3 bcd value in 100 mv bits 4 ? 7 hex value in volts 46: --c0 12.0v
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 73 table c9. protection register information table c10. burst read information table c11. partition and erase-block region information (1) length description hex p = 39h (optional flash features and commands) add. code value (p+e)h 1 number of protection register fields in jedec id space. ? 00h, ? indicates that 256 protection fields are available 47: --01 1 (p+f)h 4 protection field 1: protection description 48: --80 80h (p+10)h this field describes user-available one time programmable 49: --00 00h (p+11)h (otp) protection register bytes. some are pre-programmed 4a: --03 8 byte (p+12)h with device-unique serial numbers. others are user programmable. bits 0 ? 15 point to the protection register lock byte, the section ? s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0 ? 7 = lock/bytes jedec-plane physical low address bits 8 ? 15 = lock/bytes jedec-plane physical high address bits 16 ? 23 = ? n ? such that 2n = factory pre-programmed bytes bits 24 ? 31 = ? n ? such that 2n = user programmable bytes 4b: --03 8 byte (1) length description hex p = 39h (optional flash features and commands) add. code value (p+13)h 1 page mode read capability bits 0 ? 7 = ? n ? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no 4c: --03 8 byte (p+14)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 4d: --03 3 (p+15)h 1 synchronous mode read capability configuration 1 bits 3 ? 7 = reserved bits 0 ? 2 ? n ? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device ? s burstable address space. this field ? s 3-bit value can be written directly to the read configuration register bits 0 ? 2 if the device is configured for its maximum word width. see offset 28h for 4e: --01 4 (p+16)h 1 synchronous mode read capability configuration 2 4f: --02 8 (p+17)h 1 synchronous mode read capability configuration 3 50: --07 cont bottom top see table below (1) (1) description address p = 39h p = 39h (optional flash features and commands) len bot top (p+18)h (p+18)h number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. 1 51: 51:
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 74 preliminary partition region 1 information (1) see table below p = 39h description address bottom top (optional flash features and commands) len bot top (p+19)h (p+19)h number of identical partitions within the partition region 2 52: 52: (p+1a)h (p+1a)h 53: 53: (p+1b)h (p+1b)h 1 54: 54: (p+1c)h (p+1c)h 1 55: 55: (p+1d)h (p+1d)h 1 56: 56: (p+1e)h (p+1e)h 1 57: 57: (p+1f)h (p+1f)h partition region 1 erase block region 1 information 4 58: 58: (p+20)h (p+20)h bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 59: 59: (p+21)h (p+21)h bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 5a: 5a: (p+22)h (p+22)h 5b: 5b: (p+23)h (p+23)h partition 1 (erase region 1) 25c:5c: (p+24)h (p+24)h minimum block erase cycles x 1000 5d: 5d: (p+25)h (p+25)h 1 5e: 5e: (p+26)h (p+26)h 1 5f: 5f: (p+27)h partition region 1 erase block region 2 information 4 60: (p+28)h bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 61: (p+29)h bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 62: (p+2a)h (bottom parameter device only) 63: (p+2b)h partition 1 (erase region 2) minimum block erase cycles x 1000 2 64: (p+2c)h (bottom parameter device only) 65: (p+2d)h 1 66: (p+2e)h 1 67: simultaneous program and erase operations allowed in other partitions while a partition in this region is in program mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations simultaneous program and erase operations allowed in other partitions while a partition in this region is in read mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations simultaneous program and erase operations allowed in other partitions while a partition in this region is in erase mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations partitions' erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in ? bulk ? x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one partition 1 (erase region 1) bits per cell; internal error correction bits 0 ? 3 = bits per cell in erase region bit 4 = reserved for ? internal ecc used ? (1=yes, 0=no) bits 5 ? 7 = reserve for future use partition 1 (erase region 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) partition 1 (erase region 2) bits per cell (bottom parameter device only) bits 0 ? 3 = bits per cell in erase region bit 4 = reserved for ? internal ecc used ? (1=yes, 0=no) bits 5 ? 7 = reserve for future use partition 1 (erase region 2) pagemode and synchronous mode capabilities defined in table 10 (bottom parameter device only) bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no)
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 preliminary 75 partition region 2 information (1) see table below p = 39h description address bottom top (optional flash features and commands) len bot top (p+2f)h (p+27)h number of identical partitions within the partition region 2 68: 60: (p+30)h (p+28)h 69: 61: (p+31)h (p+29)h 1 6a: 62: (p+32)h (p+2a)h 1 6b: 63: (p+33)h (p+2b)h 1 6c: 64: (p+34)h (p+2c)h 1 6d: 65: (p+35)h (p+2d)h partition region 2 erase block region 1 information 4 6e: 66: (p+36)h (p+2e)h bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 6f: 67: (p+37)h (p+2f)h bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 70: 68: (p+38)h (p+30)h 71: 69: (p+39)h (p+31)h partition 2 (erase region 1) 2 72: 6a: (p+3a)h (p+32)h minimum block erase cycles x 1000 73: 6b: (p+3b)h (p+33)h 1 74: 6c: (p+3c)h (p+34)h 1 75: 6d: (p+35)h partition region 2 erase block region 2 information 4 6e: (p+36)h bits 0 ? 15 = y, y+1 = number of identical-size erase blocks 6f: (p+37)h bits 16 ? 31 = z, region erase block(s) size are z x 256 bytes 70: (p+38)h (top parameter device only) 71: (p+39)h partition 2 (erase region 2) minimum block erase cycles x 1000 2 72: (p+3a)h (top parameter device only) 73: (p+3b)h 1 74: (p+3c)h 1 75: (p+3d)h (p+3d)h features space definitions (reserved for future use) tbd 76: 76: (p+3e)h (p+3e)h reserved for future use resv'd 77: 77: simultaneous program and erase operations allowed in other partitions while a partition in this region is in program mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations simultaneous program and erase operations allowed in other partitions while a partition in this region is in read mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations partition 2 (erase region 2) bits per cell (top parameter only) bits 0 ? 3 = bits per cell in erase region bit 4 = reserved for ? internal ecc used ? (1=yes, 0=no) bits 5 ? 7 = reserve for future use partition 2 (erase region 2) pagemode and synchronous mode capabilities as defined in table 10. (top parameter only) bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) simultaneous program and erase operations allowed in other partitions while a partition in this region is in erase mode bits 0 ? 3 = number of simultaneous program operations bits 4 ? 7 = number of simultaneous erase operations partitions' erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in ? bulk ? x = number of erase block regions w/ contiguous same-size partition 2 (erase region 1) bits per cell bits 0 ? 3 = bits per cell in erase region bit 4 = reserved for ? internal ecc used ? (1=yes, 0=no) bits 5 ? 7 = reserve for future use partition 2 (erase region 1) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no)
28f6408w30, 28f3204w30, 28f320w30, 28f640w30 76 preliminary partition and erase-block region information notes: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. for a 16mb the 1.8 volt intel ? wireless flash memory z1 = 0100h = 256 ? 256 * 256 = 64k, y1 = 17h = 23d ? y1+1 = 24 ? 24 * 64k = 1 ? mb ? partition 2 ? s offset is 0018 0000h bytes (000c 0000h words). 3. tpd - top parameter device; bpd - bottom parameter device. 4. partition: each partition is 4mb in size. it can contain main blocks or a combination of both main and parameter blocks. 5. partition region: symmetrical partitions form a partition region. (there are two partition regions, a. contains all the partitions that are made up of main blocks only. b. contains the partition that is made up of the parameter and the main blocks. address 16 mbit 32 mbit ? b ? t ? b ? t ? b ? t ? b ? t 51: --02 --02 --02 --02 --02 --02 --02 --02 52: --01 --03 --01 --07 --01 --0f --01 --1f 53: --00 --00 --00 --00 --00 --00 --00 --00 54: --01 --01 --01 --01 --01 --01 --01 --01 55: --00 --00 --00 --00 --00 --00 --00 --00 56: --00 --00 --00 --00 --00 --00 --00 --00 57: --02 --03 --02 --07 --02 --f --02 --1f 58: --07 --07 --07 --07 --07 --07 --07 --07 59: --00 --00 --00 --00 --00 --00 --00 --00 5a: --20 --00 --20 --00 --20 --00 --20 --00 5b: --00 --01 --00 --01 --00 --01 --00 --01 5c: --64 --64 --64 --64 --64 --64 --64 --64 5d: --00 --00 --00 --00 --00 --00 --00 --00 5e: --01 --01 --01 --01 --01 --01 --01 --01 5f: --02 --03 --02 --03 --02 --03 --02 --03 60: --06 --01 --06 --01 --06 --01 --06 --01 61: --00 --00 --00 --00 --00 --00 --00 --00 62: --00 --01 --00 --01 --00 --01 --00 --01 63: --01 --00 --01 --00 --01 --00 --01 --00 64: --64 --00 --64 --00 --64 --00 --64 --00 65: --00 --02 --00 --02 --00 --02 --00 --02 66: --01 --06 --01 --06 --01 --06 --01 --06 67: --03 --00 --03 --00 --03 --00 --03 --00 68: --03 --00 --07 --00 --0f --00 --1f --00 69: --00 --01 --00 --01 --00 --01 --00 --01 6a: --01 --64 --01 --64 --01 --64 --01 --64 6b: --00 --00 --00 --00 --00 --00 --00 --00 6c: --00 --01 --00 --01 --00 --01 --00 --01 6d: --03 --03 --07 --03 --f --03 --1f --03 6e: --07 --07 --07 --07 --07 --07 --07 --07 6f: --00 --00 --00 --00 --00 --00 --00 --00 70: --00 --20 --00 --20 --00 --20 --00 --20 71: --01 --00 --01 --00 --01 --00 --01 --00 72: --64 --64 --64 --64 --64 --64 --64 --64 73: --00 --00 --00 --00 --00 --00 --00 --00 74: --01 --01 --01 --01 --01 --01 --01 --01 75: --03 --02 --03 --02 --03 --02 --03 --02 64mbit 128mbit

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